verilog用if语句设计一个全加器

你好！感谢你的提问。关于Verilog用if语句设计全加器的问题，以下是一个简单的Verilog代码：

module full_adder(input a, input b, input c_in, output sum, output c_out);
  reg s; //sum bit holding register
  reg c; //carry bit holding register
  
  always @ (a, b, c_in) begin
    if(a & b & c_in) begin
      s <= 1;
      c <= 1;
    end else if(a & b) begin
      s <= 0;
      c <= 1;
    end else if(a & c_in) begin
      s <= 0;
      c <= 1;
    end else if(b & c_in) begin
      s <= 0;
      c <= 1;
    end else if(a) begin
      s <= 1;
      c <= 0;
    end else if(b) begin
      s <= 1;
      c <= 0;
    end else if(c_in) begin
      s <= 1;
      c <= 0;
    end else begin
      s <= 0;
      c <= 0;
    end
  end
  
  assign sum = s;
  assign c_out = c;
endmodule

希望对你有所帮助！如果有其他问题，欢迎随时向我提问。