使用verilog语言编写一个4-16译码器

使用Verilog语言编写4-16译码器可以通过定义4个输入信号和16个输出信号来实现，具体的编程代码如下： module DECODER (A, B, C, D, O);
input A, B, C, D;
output [15:0] O;
reg [15:0] O; always @(A or B or C or D)
begin
case ({A, B, C, D})
4'b0000: O = 16'b0001;
4'b0001: O = 16'b0010;
4'b0010: O = 16'b0100;
4'b0011: O = 16'b1000;
4'b0100: O = 16'b0001;
4'b0101: O = 16'b0010;
4'b0110: O = 16'b0100;
4'b0111: O = 16'b1000;
4'b1000: O = 16'b0001;
4'b1001: O = 16'b0010;
4'b1010: O = 16'b0100;
4'b1011: O = 16'b1000;
4'b1100: O = 16'b0001;
4'b1101: O = 16'b0010;
4'b1110: O = 16'b0100;
4'b1111: O = 16'b1000;
default: O = 16'b0000;
endcase
endendmodule