vhdl led计时器
时间: 2024-01-17 10:04:03 浏览: 36
下面是一个简单的VHDL代码,实现LED计时器:
```vhdl
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity led_timer is
port (
clk : in std_logic;
reset : in std_logic;
led : out std_logic
);
end entity led_timer;
architecture rtl of led_timer is
signal counter : unsigned(23 downto 0) := (others => '0');
begin
process(clk, reset)
begin
if reset = '1' then
counter <= (others => '0');
led <= '0';
elsif rising_edge(clk) then
counter <= counter + 1;
if counter = 100000000 then -- 100MHz / 100000000 = 1s
counter <= (others => '0');
led <= not led;
end if;
end if;
end process;
end architecture rtl;
```
该代码使用一个计数器来计时,当计数器达到1秒时,LED状态会翻转。你可以根据需要修改计数器的初始值和计时周期,以满足你的需求。