用verilog给我一个SPI接口代码

module spi_interface(
input wire clk,
input wire rst,
input wire cs_n,
output reg mosi,
input wire miso,
input wire sclk
);

// Internal states
parameter IDLE = 2'b00;
parameter SHIFT_OUT = 2'b01;
parameter SHIFT_IN = 2'b10;
parameter DONE = 2'b11;

reg [1:0] state;
reg [7:0] tx_data;
reg [7:0] rx_data;
reg [7:0] bit_count;

// Initialize internal states
initial begin
state = IDLE;
end

// Reset the SPI interface
always @(posedge rst) begin
state <= IDLE;
bit_count <= 0;
tx_data <= 0;
rx_data <= 0;
end

// Clock the SPI interface
always @(posedge clk) begin
case (state)
IDLE: begin
if (!cs_n) begin
mosi <= 0;
bit_count <= 0;
state <= SHIFT_OUT;
end
end
SHIFT_OUT: begin
mosi <= tx_data[bit_count];
bit_count <= bit_count + 1;
if (bit_count == 8) begin
bit_count <= 0;
state <= SHIFT_IN;
end
end
SHIFT_IN: begin
rx_data[bit_count] <= miso;
bit_count <= bit_count + 1;
if (bit_count == 8) begin
bit_count <= 0;
state <= DONE;
end
end
DONE: begin
mosi <= 0;
state <= IDLE;
end
endcase
end

// Assign the output data
always @(posedge clk) begin
if (state == DONE && !cs_n) begin
mosi <= 0;
rx_data <= 0;
end
end

// Assign the input data
assign rx_data = (state == DONE && !cs_n) ? rx_data : 8'hzz;

endmodule