Error: E:/modelsim/examples/monitor.v(22): Register is illegal in left-hand side of continuous assignment
时间: 2024-02-02 10:02:36 浏览: 203
这个错误是因为在 continuous assignment(连续赋值)语句中使用了寄存器类型的变量作为左值。在 SystemVerilog 中,寄存器类型的变量只能在过程块中赋值,不能在连续赋值语句中使用。你需要将寄存器类型的变量改为 wire 类型的变量,或者将连续赋值语句改为 always 块中的赋值语句。
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