设计一个多功能流水灯控制器，实现如下花样流水效果。如果用频率10HZ 的时钟来驱动电 路，则用10个时钟周期可以实现 1s的延迟。 ，从左向右逐个点亮灯，不断循环; ，花样流水灯，从右向左逐个点亮灯，不断循环； ，花样流水灯， •从两头向中间逐个点亮灯，不断 循环； ，花样流水灯，从中间向两头逐个点亮灯，不断循环的四个实验代码

好的，下面是这四种效果的代码实现，假设使用FPGA的时钟频率为100MHz:

1. 从左向右逐个点亮灯，不断循环

module led_controller (
    input clk, // 时钟信号
    output reg [7:0] led // LED输出信号
);

reg [3:0] counter;

always @(posedge clk) begin
    counter <= counter + 1;
    if (counter == 4'd9) begin
        counter <= 4'd0;
        led <= {led[6:0], led[7]};
    end
end

endmodule

2. 花样流水灯，从右向左逐个点亮灯，不断循环

module led_controller (
    input clk, // 时钟信号
    output reg [7:0] led // LED输出信号
);

reg [3:0] counter;

always @(posedge clk) begin
    counter <= counter + 1;
    if (counter == 4'd9) begin
        counter <= 4'd0;
        led <= {led[0], led[7:1]};
    end
end

endmodule

3. 花样流水灯，从两头向中间逐个点亮灯，不断循环

module led_controller (
    input clk, // 时钟信号
    output reg [7:0] led // LED输出信号
);

reg [3:0] counter;

always @(posedge clk) begin
    counter <= counter + 1;
    if (counter == 4'd9) begin
        counter <= 4'd0;
        led <= ~(counter == 4'd0 || counter == 4'd8) ? {led[1:0], 6'b0} :
               ~(counter == 4'd1 || counter == 4'd7) ? {led[2:0], 5'b0} :
               ~(counter == 4'd2 || counter == 4'd6) ? {led[3:0], 4'b0} :
               ~(counter == 4'd3 || counter == 4'd5) ? {led[4:0], 3'b0} :
                                                        {led[5:0], 2'b0};
    end
end

endmodule

4. 花样流水灯，从中间向两头逐个点亮灯，不断循环

module led_controller (
    input clk, // 时钟信号
    output reg [7:0] led // LED输出信号
);

reg [3:0] counter;

always @(posedge clk) begin
    counter <= counter + 1;
    if (counter == 4'd9) begin
        counter <= 4'd0;
        led <= ~(counter == 4'd0 || counter == 4'd8) ? {led[5:0], 2'b0} :
               ~(counter == 4'd1 || counter == 4'd7) ? {led[4:0], 3'b0} :
               ~(counter == 4'd2 || counter == 4'd6) ? {led[3:0], 4'b0} :
               ~(counter == 4'd3 || counter == 4'd5) ? {led[2:0], 5'b0} :
                                                        {led[1:0], 6'b0};
    end
end

endmodule

以上代码仅供参考，具体实现方式可能因硬件平台和需求不同而有所差异。