分别生成单口RAM和伪双口RAM的verilog 代码

好的，下面是单口RAM和伪双口RAM的Verilog代码示例：

1. 单口RAM的Verilog代码示例：

module SinglePortRAM (
    input wire clk,
    input wire write_en,
    input wire [7:0] write_data,
    input wire [3:0] address,
    output reg [7:0] read_data
);

reg [7:0] mem [15:0];

always @(posedge clk) begin
    if (write_en)
        mem[address] <= write_data;
    read_data <= mem[address];
end

endmodule

2. 伪双口RAM的Verilog代码示例：

module DualPortRAM (
    input wire clk,
    input wire write_en_A,
    input wire write_en_B,
    input wire [7:0] write_data_A,
    input wire [7:0] write_data_B,
    input wire [3:0] address_A,
    input wire [3:0] address_B,
    output reg [7:0] read_data_A,
    output reg [7:0] read_data_B
);

reg [7:0] mem [15:0];

always @(posedge clk) begin
    if (write_en_A)
        mem[address_A] <= write_data_A;
    if (write_en_B)
        mem[address_B] <= write_data_B;
    read_data_A <= mem[address_A];
    read_data_B <= mem[address_B];
end

endmodule

以上是单口RAM和伪双口RAM的Verilog代码示例，可根据需要进行修改和扩展。