同步置1异步清0的D触发器EDA代码
时间: 2024-02-03 15:02:59 浏览: 118
以下是同步置1异步清0的D触发器的EDA代码:
```vhdl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity DFF1 is
Port ( CLK, CLR, SET, D : in STD_LOGIC;
Q : out STD_LOGIC);
end DFF1;
architecture Behavioral of DFF1 is
begin
process (CLK, CLR)
begin
if CLR = '1' then
Q <= '0';
elsif rising_edge(CLK) then
if SET = '1' then
Q <= '1';
else
Q <= D;
end if;
end if;
end process;
end Behavioral;
```
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