virtual interface
时间: 2023-10-31 10:04:38 浏览: 45
Virtual interface是一种在Verilog和SystemVerilog中使用的概念。它允许在仿真运行时动态连接到设备(DUT)上,而不需要在编译时进行连接。Virtual interface本质上是指向interface的指针,而interface是一个真实存在的实体。它的主要作用是完成接口的动态分配,可以简化模块之间的连接,并且可以消除绝对路径的使用,从而减少在修改时需要改变的内容。在基于OOP的测试平台中,使用virtual interface可以实现对DUT的操作和激励传送。<span class="em">1</span><span class="em">2</span><span class="em">3</span>
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- *1* [【SystemVerilog基础】virtual interface 实用总结](https://blog.csdn.net/ReCclay/article/details/123661616)[target="_blank" data-report-click={"spm":"1018.2226.3001.9630","extra":{"utm_source":"vip_chatgpt_common_search_pc_result","utm_medium":"distribute.pc_search_result.none-task-cask-2~all~insert_cask~default-1-null.142^v93^chatsearchT3_2"}}] [.reference_item style="max-width: 50%"]
- *2* *3* [System Verilog学习笔记—虚接口(virtual interface)](https://blog.csdn.net/qq_41337361/article/details/122024392)[target="_blank" data-report-click={"spm":"1018.2226.3001.9630","extra":{"utm_source":"vip_chatgpt_common_search_pc_result","utm_medium":"distribute.pc_search_result.none-task-cask-2~all~insert_cask~default-1-null.142^v93^chatsearchT3_2"}}] [.reference_item style="max-width: 50%"]
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