module test; genvar i; generate for (i=0; i<3; i++) begin: INST test INST (.a(a[i]), .b(b[i]),.c(c[i]),); end endgenerate module test; typedef struct packed { logic [9:-1][2:0] a; ///REQ-EXT-10001, REQ-EXT-10004 } ST1; typedef struct { ST1 st1; ST1 st2[2:0]; }ST2; initial begin ST2 st2; st2 = '{2'b01, '{3'b1, 3'b0, 12'b1}}; $display("%", st2); //CHECK-001:'{a:'h1}, st2:'{'a:'h1}, '{a:'h0},'{a:h1}}} end endmodule when compiled by vcs, it reports Parsing design file 'sc_assignment_pattern_033.sv' Error-[MPC] Mixed port connection is not allowed sc_assignment_pattern_033.sv, 17 The two types of module port connections, by ordered list and by name, shall not be mixed. Please refer to Verilog LRM(1364-2001), section 12.3.6. How should I fix this error so that it can be compiled successfully by vcs? thanks a lot.

The error message indicates that mixed port connection is not allowed in Verilog. In your code, you are using both ordered list and named port connection in the instantiation of module "test".

To fix this error, you can either use ordered list connection for all module ports or named port connection for all module ports. Here is an example of how to use named port connection:

module test (
  input [2:0] a,
  input [2:0] b,
  output [2:0] c
);

// module implementation

endmodule

module top;

logic [2:0] a, b, c;

test INST (
  .a(a),
  .b(b),
  .c(c)
);

endmodule

In the above example, all module ports are connected using named port connection. You can apply this to your code accordingly.