module test_top; genvar i; generate for (i=0; i<3; i++) begin: INST module test; typedef struct packed { logic [9:-1][2:0] a; ///REQ-EXT-10001, REQ-EXT-10004 } ST1; typedef struct { ST1 st1; ST1 st2[2:0]; }ST2; initial begin ST2 st2; st2 = '{2'b01, '{3'b1, 3'b0, 12'b1}}; $display("%", st2); //CHECK-001:'{a:'h1}, st2:'{'a:'h1}, '{a:'h0},'{a:h1}}} end end endgenerate endmodule when compiled by vcs, it says following verilog source has syntax error: "sc_assignment_pattern_033.sv",17: token is 'module' module test; how should I fix this syntax error so that this piece of system verilog code can be compiled successfully by vcs? thanks a lot.

The syntax error is likely caused by the fact that you have a nested module definition within your generate block. In SystemVerilog, nested modules are not allowed. To fix this error, you can move the module definition outside of the generate block and instantiate it within the generate block. Here's an example of how you can modify your code:

module test;
  // Define your typedefs here

  // Instantiate your module within the generate block
  genvar i;
  generate
    for (i = 0; i < 3; i++) begin : INST
      test INST (.a(a[i]), .b(b[i]), .c(c[i]));
    end
  endgenerate

  // Define your inputs and outputs here
  logic [3:0] a;
  logic [3:0] b;
  logic [3:0] c;

  // Define your module logic here
  // ...

endmodule

In this example, the module definition is moved outside of the generate block and instantiated within the generate block using the `test INST` syntax. This should resolve the syntax error and allow your code to be compiled successfully by vcs.