四位全加器verilog代码

以下是一个四位全加器的 Verilog 代码示例：

module full_adder_4bit(A, B, Cin, Sum, Cout);
input [3:0] A, B;
input Cin;
output [3:0] Sum;
output Cout;

wire [3:0] carry;
wire [3:0] s;

full_adder fa0(A[0], B[0], Cin, s[0], carry[0]);
full_adder fa1(A[1], B[1], carry[0], s[1], carry[1]);
full_adder fa2(A[2], B[2], carry[1], s[2], carry[2]);
full_adder fa3(A[3], B[3], carry[2], s[3], Cout);

assign Sum = s;

endmodule

module full_adder(A, B, Cin, Sum, Cout);
input A, B, Cin;
output Sum, Cout;

assign Sum = A ^ B ^ Cin;
assign Cout = (A & B) | (A & Cin) | (B & Cin);

endmodule

这个代码中包含了一个 `full_adder` 模块，用来实现单个全加器的功能，以及一个 `full_adder_4bit` 模块，用来将四个全加器连接起来，实现四位全加器的功能。

相关问题

四位全加器verilog仿真

好的，以下是四位全加器的 Verilog 代码和仿真结果：

module full_adder(
    input a,
    input b,
    input cin,
    output sum,
    output cout
);

assign sum = a ^ b ^ cin;
assign cout = (a & b) | (a & cin) | (b & cin);

endmodule

module four_bit_adder(
    input [3:0] a,
    input [3:0] b,
    input cin,
    output [3:0] sum,
    output cout
);

wire c1, c2, c3;

full_adder fa0(a[0], b[0], cin, sum[0], c1);
full_adder fa1(a[1], b[1], c1, sum[1], c2);
full_adder fa2(a[2], b[2], c2, sum[2], c3);full_adder fa3(a[3], b[3], c3, sum[3], cout);

endmodule

仿真结果如下图所示：


四位全加器verilog仿真激励

以下是四位全加器的Verilog代码和仿真激励：

module full_adder(
    input a,
    input b,
    input cin,
    output sum,
    output cout
);

assign sum = a ^ b ^ cin;
assign cout = (a & b) | (a & cin) | (b & cin);

endmodule

module four_bit_adder(
    input [3:0] a,
    input [3:0] b,
    input cin,
    output [3:0] sum,
    output cout
);

wire c1, c2, c3;

full_adder fa0(a[0], b[0], cin, sum[0], c1);
full_adder fa1(a[1], b[1], c1, sum[1], c2);
full_adder fa2(a[2], b[2], c2, sum[2], c3);
full_adder fa3(a[3], b[3], c3, sum[3], cout);

endmodule

module testbench();

reg [3:0] a;
reg [3:0] b;
reg cin;
wire [3:0] sum;
wire cout;

four_bit_adder dut(a, b, cin, sum, cout);

initial begin
    a = 4'b0000;
    b = 4'b0000;
    cin = 0;
    
    #10 a = 4'b0001; b = 4'b0001;
    #10 a = 4'b0010; b = 4'b0010;
    #10 a = 4'b0100; b = 4'b0100;
    #10 a = 4'b1000; b = 4'b1000;
    
    #10 a = 4'b1111; b = 4'b0001;
    #10 a = 4'b1111; b = 4'b0010;
    #10 a = 4'b1111; b = 4'b0100;
    #10 a = 4'b1111; b = 4'b1000;
    
    #10 a = 4'b1010; b = 4'b0101;
    #10 a = 4'b1100; b = 4'b0011;
    #10 a = 4'b1111; b = 4'b1111;
    
    #10 a = 4'b0111; b = 4'b1000;
    #10 a = 4'b0001; b = 4'b1111;
    
    #10 a = 4'b1010; b = 4'b0101; cin = 1;
    #10 a = 4'b1100; b = 4'b0011; cin = 1;
    #10 a = 4'b1111; b = 4'b1111; cin = 1;
    
    #10 a = 4'b0111; b = 4'b1000; cin = 1;
    #10 a = 4'b0001; b = 4'b1111; cin = 1;
end

endmodule

仿真结果如下：