根据输入信号a,b的大小关系，求解两个数的差值：输入信号a,b为8bit位宽的无符号数。如果a>b，则输出a-b，如果a≤b，则输出b-a。使用Verilog HDL实现以上功能并编写testbench验证。

module diff (
input [7:0] a,
input [7:0] b,
output [7:0] diff
);

assign diff = (a>b) ? a-b : b-a;

endmodule

module testbench;

reg [7:0] a;
reg [7:0] b;
wire [7:0] diff;

diff dut(
.a(a),
.b(b),
.diff(diff)
);

initial begin
$dumpfile("diff.vcd");
$dumpvars(0, testbench);

a = 5;
b = 10;
#10;
$display("a=%d, b=%d, diff=%d", a, b, diff);

a = 15;
b = 10;
#10;
$display("a=%d, b=%d, diff=%d", a, b, diff);

a = 0;
b = 255;
#10;
$display("a=%d, b=%d, diff=%d", a, b, diff);

a = 255;
b = 0;
#10;
$display("a=%d, b=%d, diff=%d", a, b, diff);

$finish;
end

endmodule