0100序列检测器verilog代码及仿真

下面是一个简单的 0100 序列检测器的 Verilog 代码及仿真：

module seq_detector(input clk, input reset, input data, output reg detected);

    reg [1:0] state; // 状态寄存器
    parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;
    // 定义状态常量

    always @(posedge clk, posedge reset)
    begin
        if (reset)
            state <= S0; // 复位状态
        else
            case (state)
                S0: if (data == 0) state <= S0; else state <= S1;
                S1: if (data == 1) state <= S2; else state <= S0;
                S2: if (data == 0) state <= S3; else state <= S1;
                S3: if (data == 0) state <= S0; else state <= S1;
            endcase
    end

    assign detected = (state == S3); // 当检测到 0100 时输出高电平

endmodule

仿真测试代码：

module seq_detector_tb();

    reg clk, reset, data;
    wire detected;

    seq_detector dut(clk, reset, data, detected);

    initial begin
        clk = 0;
        reset = 1;
        data = 0;
        #10 reset = 0;

        repeat(4) begin
            #5 data = 0;
            #5 data = 1;
            #5 data = 0;
            #5 data = 0;
        end

        #10 $finish;
    end

    always #5 clk = ~clk;

endmodule

在仿真中，输入数据为 0100，输出 detected 信号应该在第四个时钟周期后变为高电平。