写一个用vhdl调用vhdl写的与门，或门，异或门所写的全加器

在VHDL中，全加器通常用于将两个二进制数相加，同时考虑一个进位输入。这里我会为你展示一个简单的全加器，使用了与门(`AND`), 或门(`OR`) 和 异或门(`XOR`)。首先，我们将分别定义与门、或门和异或门，然后组合它们实现全加器。

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- 定义与门
entity AND_gate is
    Port ( A, B: in STD_LOGIC;
           Y : out STD_LOGIC);
end AND_gate;

architecture Behavioral of AND_gate is
begin
    Y <= A and B;
end Behavioral;

-- 定义或门
entity OR_gate is
    Port ( A, B: in STD_LOGIC;
           Y : out STD_LOGIC);
end OR_gate;

architecture Behavioral of OR_gate is
begin
    Y <= A or B;
end Behavioral;

-- 定义异或门
entity XOR_gate is
    Port ( A, B: in STD_LOGIC;
           Y : out STD_LOGIC);
end XOR_gate;

architecture Behavioral of XOR_gate is
begin
    Y <= not(A xor B);
end Behavioral;

-- 全加器部分
entity Full_adder is
    Port (
        A, B: in STD_LOGIC; -- 加法输入
        Cin: in STD_LOGIC; -- 进位输出
    );
end Full_adder;

architecture Behavioral of Full_adder is
begin
    Sum <= A xor B xor Cin; -- 和
    Carry_out <= (A and B) or (A and Cin) or (B and Cin); -- 进位
end Behavioral;

-- 使用上述部件构建全加器
entity TopLevelDesign is
    Port (
        Data_in_0, Data_in_1: in STD_LOGIC;
        Carry_in: in STD_LOGIC;
        Sum_out, Carry_out: out STD_LOGIC;
    );
end TopLevelDesign;

architecture Behavioral of TopLevelDesign is
    component AND_gate is end AND_gate;
    component OR_gate is end OR_gate;
    component XOR_gate is end XOR_gate;
    component Full_adder is end Full_adder;

    -- 实例化与门、或门、异或门和全加器
    Full_adder FA (A => Data_in_0, B => Data_in_1, Cin => Carry_in,
                 Sum => Sum_out(1 downto 0), Carry_out => Carry_out);

    -- 如果有更多位宽的全加器，需适当调整Sum_out的宽度
end Behavioral;

-- 相关问题:
1. 全加器的工作原理是什么？
2. 如何用VHDL实现一个多位的全加器链？
3. VHDL中如何处理全加器的错误或异常情况？