module jsq_ctrl (clk,rst_n,data,en,sum,ENA,flag_sum,led); input clk; //50mhz周期20ns input rst_n; input [3:0] data; //按键值 input en; //按键的使能信号 //1ms output reg ENA; output reg [15:0] sum;//计算结果 output reg flag_sum; //结果是否有问题信号 output reg led； reg [15:0] mima; reg [2:0] cnt; reg [2:0] wrong; reg m; //对输入的键值进行同步处理 reg en1,en2; wire flag; always @ (posedge clk ,negedge rst_n) begin if (!rst_n) begin en1 <= 1'b0; en2 <= 1'b0; end else begin en1 <= en; en2 <= en1; end end assign flag = en1 &(~en2); //检测上升沿 //计算过程的执行 reg [2:0] state; reg [23:0] a; reg [23:0] sum1; reg flag_out; reg flag_en; //不需要转化的输出数据 always @ (posedge clk,negedge rst_n) begin if (!rst_n) begin a <= 24'd0; sum1 <= 24'd0; flag_out <= 1'b0; flag_sum <= 1'b0; flag_en <= 1'b0; cnt<=0; wrong<=0; ENA<=0; led<=1; m<=0; end else if (flag) begin if (data >= 4'd0 && data <= 4'h9) begin a <= {a[19:0],data}; sum1 <= {a[19:0],data}; flag_out <= 1'b1; flag_en <= 1'b1; end else if (data == 4'ha) //清零键 begin flag_out <= 1'b1; sum1 <= 24'd0; a <= 24'h0; flag_en <= 1'b0; end else if (data == 4'hb) //=键 begin if(!m) begin mima=sum1[15:0]; sum1 <= 24'd0; a <= 24'h0; m=1; flag_en <= 1'b1; flag_out <= 1'b1; end else if(sum1[15:0]==mima) begin led<=0; a <= 24'h0; wrong<=0; flag_en <= 1'b1; flag_out <= 1'b1; sum1 <= 24'd0; end else if(mima!=sum1[15:0]) begin if(wrong<2) begin a <= 24'h0; flag_en <= 1'b1; flag_out <= 1'b1; wrong<=wrong+1; sum1 <= 24'd0; end else begin a <= 24'h0; ENA<=1; wrong<=0; flag_en <= 1'b0; sum1<=0; flag_out <= 1'b1; end end end end else begin a <= a; sum1 <= sum1; flag_out <= 1'b0; flag_sum <= 1'b0; flag_en <= flag_en; end end //输出算数结果 always @ (posedge clk,negedge rst_n) begin if (!rst_n) sum <= 24'h0; else if (flag_en) sum <= sum1; else if (flag_out) begin sum[3:0] <= sum1 % 10; sum[7:4] <= sum1 / 10 % 10; sum[11:8] <= sum1 / 100 % 10; sum[15:12] <= sum1 / 1000 % 10; ENA <= ENA; end else sum <= sum; end endmodule

根据您提供的FPGA代码，我为您生成了对应的testbench文件。请注意，生成的testbench文件可能需要根据您的测试需求进行进一步修改和完善。

`timescale 1ns / 1ps

module jsq_ctrl_tb;

	reg clk;
	reg rst_n;
	reg [3:0] data;
	reg en;
	wire ENA;
	wire [15:0] sum;
	wire flag_sum;
	wire led;

	jsq_ctrl uut (
		.clk(clk),
		.rst_n(rst_n),
		.data(data),
		.en(en),
		.sum(sum),
		.ENA(ENA),
		.flag_sum(flag_sum),
		.led(led)
	);

	initial begin
		clk = 0;
		rst_n = 0;
		data = 0;
		en = 0;

		#10 rst_n = 1; // Release reset
	end

	always #10 clk = ~clk;

	initial begin
		// Testcase 1
		data = 4; // Assign input values
		en = 1;
		#100; // Wait for calculation
		en = 0; // Disable input
		#100;

		// Testcase 2
		data = 10; // Assign input values
		en = 1;
		#100; // Wait for calculation
		en = 0; // Disable input
		#100;

		// Testcase 3
		data = 11; // Assign input values
		en = 1;
		#100; // Wait for calculation
		en = 0; // Disable input
		#100;

		// Add more testcases as needed
	end

endmodule

请根据您的需求修改并使用此生成的testbench文件进行仿真测试。如果有任何问题或需要进一步的帮助，请随时告诉我。