interface Int(); class t1; integer a[string]; //REQ-EXT-10007 function new; //class constructor body need be modified according to REQ-EXT-10007 a = '{"a":40, "b":60, "c":80}'; endfunction endclass class t2; integer b[string]; //REQ-EXT-10007 function new; //class constructor body need be modified according to REQ-EXT-10007 b = '{"aa":44, "bb":66,"cc":88}'; endfunction endclass t1 inst1 = new; //REQ-EXT-10501 t2 inst2 = new; //REQ-EXT-10501 endinterface module top; Int in(); virtual Int testint = in; associative my_array[string]; // Renamed variable "array" to "my_array" initial begin #1; my_array = testint.inst1.a; $display("testint.inst1.a = %p", testint.inst1.a); //CHECK-001:'{"a":40, "b":60, "c":80} $display("my_array = %p", my_array); //CHECK-002:'{"a":40, "b":60, "c":80} #2; my_array = testint.inst2.b; $display("testint.inst2.b = %p", testint.inst2.b); //CHECK-003:'{"aa":44, "bb":66,"cc":88} $display("my_array = %p", my_array); //CHECK-004:'{"aa":44, "bb":66,"cc":88} end endmodule this piece of system verilog code, when compiled by vcs, will report syntax error:38: token is ';', how should I fix this syntax error? thanks a lot

The syntax error is caused by the empty parentheses in the definition of interface Int(). To fix this error, you should remove the empty parentheses from the interface definition. The corrected code should be:

interface Int;
class t1;
integer a[string]; //REQ-EXT-10007
function new;
a = '{"a":40, "b":60, "c":80}';
endfunction
endclass
class t2;
integer b[string]; //REQ-EXT-10007
function new;
b = '{"aa":44, "bb":66,"cc":88}';
endfunction
endclass
t1 inst1 = new; //REQ-EXT-10501
t2 inst2 = new; //REQ-EXT-10501
endinterface

After making this change, the code should compile without any syntax errors.