使用verilog设计一个状态机模拟交通信号灯

module traffic_light(
input clk, // 时钟信号
input rst, // 复位信号
output reg red, // 红灯信号
output reg yellow, // 黄灯信号
output reg green // 绿灯信号
);

// 定义状态枚举类型
typedef enum logic [1:0] {
RED_STATE,
RED_YELLOW_STATE,
GREEN_STATE,
YELLOW_STATE
} STATE;

// 定义状态寄存器和下一个状态变量
reg [1:0] state_reg, next_state;

// 初始化状态寄存器
initial begin
state_reg = RED_STATE;
end

// 状态转移逻辑
always @ (posedge clk, posedge rst) begin
if (rst) begin
state_reg <= RED_STATE;
end else begin
state_reg <= next_state;
end
end

// 输出逻辑
always @ (state_reg) begin
case(state_reg)
RED_STATE: begin
red = 1'b1;
yellow = 1'b0;
green = 1'b0;
next_state = RED_YELLOW_STATE;
end
RED_YELLOW_STATE: begin
red = 1'b1;
yellow = 1'b1;
green = 1'b0;
next_state = GREEN_STATE;
end
GREEN_STATE: begin
red = 1'b0;
yellow = 1'b0;
green = 1'b1;
next_state = YELLOW_STATE;
end
YELLOW_STATE: begin
red = 1'b0;
yellow = 1'b1;
green = 1'b0;
next_state = RED_STATE;
end
default: begin
red = 1'b0;
yellow = 1'b0;
green = 1'b0;
next_state = RED_STATE;
end
endcase
end

endmodule