请举例一个verilog三段式状态机

以下是一个简单的 Verilog 三段式状态机的例子，它描述了一个模拟的交通信号灯：

module traffic_light (
    input clk,
    output reg red,
    output reg yellow,
    output reg green
);

// 定义状态
parameter RED_STATE = 2'b00;
parameter YELLOW_STATE = 2'b01;
parameter GREEN_STATE = 2'b10;

// 定义状态寄存器和下一个状态寄存器
reg [1:0] state, next_state;

// 定义状态转换条件
wire to_yellow = (state == RED_STATE) && (next_state == YELLOW_STATE);
wire to_green = (state == YELLOW_STATE) && (next_state == GREEN_STATE);
wire to_red = (state == GREEN_STATE) && (next_state == RED_STATE);

// 状态转换逻辑
always @ (posedge clk) begin
    if (to_yellow) begin
        state <= YELLOW_STATE;
    end else if (to_green) begin
        state <= GREEN_STATE;
    end else if (to_red) begin
        state <= RED_STATE;
    end
end

// 输出逻辑
always @ (*) begin
    case (state)
        RED_STATE: begin
            red = 1;
            yellow = 0;
            green = 0;
        end
        YELLOW_STATE: begin
            red = 0;
            yellow = 1;
            green = 0;
        end
        GREEN_STATE: begin
            red = 0;
            yellow = 0;
            green = 1;
        end
        default: begin
            red = 0;
            yellow = 0;
            green = 0;
        end
    endcase
end

endmodule

这个状态机有三个状态：RED_STATE，YELLOW_STATE，GREEN_STATE。它通过时钟触发，根据下一个状态寄存器的值决定当前状态的转换。当状态转换时，相应的输出也会相应地改变。