用Python写一个统计Verilog代码行数的脚本，首先打开指定的文件并读取全部内容。然后使用正则表达式去除注释，并按行分割并去除空白字符。接下来，它统计不在模块定义、包定义、函数定义、任务定义、generate块等特殊语句内的代码行数。然后，它查找每个模块实例化语句，并递归计算每个模块的行数，将其加入总行数中。最后，它查找每个 include 语句，并递归计算每个 included 文件的行数，将其加入总行数中。最终返回总行数。也同时输出各个子模块例化名及行数，include文件的对应的代码行数

以下是一个可能的实现：

import re

def count_verilog_code(file_path):
    # 打开文件并读取全部内容
    with open(file_path, 'r') as f:
        content = f.read()
    
    # 去除注释
    content = re.sub(r'/\*[\s\S]*?\*/', '', content)
    content = re.sub(r'//.*', '', content)
    
    # 按行分割并去除空白字符
    lines = [line.strip() for line in content.split('\n')]
    
    # 统计代码行数
    total_lines = 0
    in_special_block = False
    module_instances = {}
    included_files = set()
    
    for line in lines:
        # 处理特殊语句
        if re.match(r'\s*(module|package|function|task|generate)\b', line):
            in_special_block = True
        elif re.match(r'\s*(endmodule|endpackage|endfunction|endtask|endgenerate)\b', line):
            in_special_block = False
        
        # 统计代码行数
        if not in_special_block and line != '':
            total_lines += 1
        
        # 处理模块实例化语句
        if re.match(r'\s*\w+\s+\w+\s*\(', line):
            match = re.search(r'\s*(\w+)\s+\w+\s*\(', line)
            if match:
                module_name = match.group(1)
                if module_name not in module_instances:
                    module_instances[module_name] = 0
                module_instances[module_name] += count_verilog_code(module_name + '.v')
        
        # 处理 include 语句
        if re.match(r'\s*`include\s+"(.+)"', line):
            match = re.search(r'\s*`include\s+"(.+)"', line)
            if match:
                included_file = match.group(1)
                if included_file not in included_files:
                    included_files.add(included_file)
                    total_lines += count_verilog_code(included_file)
    
    # 输出子模块例化名及行数，以及 included 文件的对应的代码行数
    print('Module instances:')
    for module_name, count in module_instances.items():
        print('- {}: {}'.format(module_name, count))
    print('Included files:')
    for included_file in included_files:
        print('- {}: {}'.format(included_file, count_verilog_code(included_file)))
    
    return total_lines

使用示例：

count = count_verilog_code('top.v')
print('Total lines of Verilog code:', count)

其中，`top.v` 是顶层模块的文件名。注意，上述实现并未考虑循环 include 的情况，如果你需要处理这种情况，可以添加相应的逻辑。