生成一个4bit位超前进位加法器verilog代码
时间: 2024-05-19 14:15:56 浏览: 10
module adder4bit_carryahead(a, b, cin, sum, cout);
input [3:0] a;
input [3:0] b;
input cin;
output [3:0] sum;
output cout;
wire [3:0] s;
wire [3:0] c;
assign s = a + b;
assign c = (a & b) | (a & cin) | (b & cin);
assign sum = s;
assign cout = c[3];
endmodule
// Testbench
module testbench;
reg [3:0] a, b;
reg cin;
wire [3:0] sum;
wire cout;
adder4bit_carryahead adder(a, b, cin, sum, cout);
initial begin
a = 4'b0000;
b = 4'b0000;
cin = 0;
#10 a = 4'b0001;
#10 b = 4'b0011;
#10 cin = 1;
#10 a = 4'b1111;
#10 b = 4'b0001;
#10 cin = 0;
#10 $finish;
end
always @(posedge clk) begin
$display("a=%b b=%b cin=%b sum=%b cout=%b", a, b, cin, sum, cout);
end
endmodule
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