给下面代码写个测试文件module fdiv10(clk,push,fdiv_10); input clk,push; output fdiv_10; reg[3:0]count10; always @(posedge clk,posedge push) begin if(push) count10<=count10; else if(count10<10) count10<=count10+1; else count10<=0; end assign fdiv_10=(count10==10)?1:0; endmodule module leds(clk,bcd1,bcd2,bcd3,bcd4,bcd5,bcd6,bcd7,bcd8,sel,a_g); input clk; input [3:0]bcd1,bcd2,bcd3,bcd4,bcd5,bcd6,bcd7,bcd8; output reg[2:0]sel; output reg[6:0]a_g; reg[3:0]temp; always @(posedge clk) begin sel<=sel+1; if(sel==5) sel<=0; end always @(sel) begin case(sel) 3'b000:temp<=bcd1; 3'b001:temp<=bcd2; 3'b010:temp<=bcd3; 3'b011:temp<=bcd4; 3'b100:temp<=bcd5; 3'b101:temp<=bcd6; 3'b110:temp<=bcd7; 3'b111:temp<=bcd8; default:temp<=bcd1; endcase case(temp) 0:a_g<=7'b1111110; //0 1:a_g<=7'b0110000; //1 2:a_g<=7'b1101101; //2 3:a_g<=7'b1111001; //3 4:a_g<=7'b0110011; //4 5:a_g<=7'b1011011; //5 6:a_g<=7'b1011111; //6 7:a_g<=7'b1110000; //7 8:a_g<=7'b1111111; //8 9:a_g<=7'b1111011; //9 default:a_g<=7'b1000111; //F endcase end endmodule module miaobiao(clk,clr,push,sel,a_g); input clk,clr,push; output[2:0]sel; output[6:0]a_g; wire push1,fdiv_10,clr1,cin2,cin4,cin6; wire[3:0]bcd1,bcd2,bcd3,bcd4,bcd5,bcd6,bcd7,bcd8; switch switchpush(clk,push,push1); switch switchclr(clk,clr,clr1); fdiv10 fdiv(clk,push1,fdiv_10); count100 count100(fdiv_10,clr1,bcd1,bcd2,cin2); count60_1 count60_1(cin2,clr1,bcd3,bcd4,cin4); count60_2 count60_2(cin4,clr1,bcd5,bcd6,cin6); count24 count24(cin6,clr1,bcd7,bcd8); leds leds(clk,bcd1,bcd2,bcd3,bcd4,bcd5,bcd6,bcd7,bcd8,sel,a_g); endmodule module switch(clk,keyin,keyout); input clk,keyin; output reg keyout; reg clk_use; reg[3:0]counter; always @(posedge clk) begin counter<=counter+1; if(counter==10) begin counter<=0; clk_use<=~clk_use; end end always @(posedge clk_use) keyout<=keyin; endmodule

下面是测试文件的代码：

`timescale 1ns / 1ps

module test_fdiv10;

reg clk, push, clr;
wire [2:0] sel;
wire [6:0] a_g;

miaobiao dut(.clk(clk), .clr(clr), .push(push), .sel(sel), .a_g(a_g));

initial begin
// test case 1: push = 0, count10 < 10
push <= 0;
clk <= 0;
clr <= 0;
#5;
assert(a_g === 7'b1111110);
assert(sel === 3'b000);

// test case 2: push = 0, count10 >= 10
push <= 0;
clk <= 0;
clr <= 0;
#60;
assert(a_g === 7'b0110011);
assert(sel === 3'b011);

// test case 3: push = 1, count10 < 10
push <= 1;
clk <= 0;
clr <= 0;
#5;
assert(a_g === 7'b1111110);
assert(sel === 3'b000);

// test case 4: push = 1, count10 >= 10
push <= 1;
clk <= 0;
clr <= 0;
#60;
assert(a_g === 7'b0110011);
assert(sel === 3'b011);

// test case 5: clr = 1
push <= 0;
clk <= 0;
clr <= 1;
#5;
assert(a_g === 7'b1000111);
assert(sel === 3'b000);

// test case 6: count100, count60_1, count60_2 count24 all reset
push <= 0;
clk <= 0;
clr <= 0;
#300;
assert(a_g === 7'b1111110);
assert(sel === 3'b000);

$display("All test cases passed.");
$finish;
end

always #5 clk <= ~clk;

endmodule`

这个测试文件会对 `miaobiao` 模块进行测试，分别测试 `fdiv10`、`count100`、`count60_1`、`count60_2` 和 `count24` 的正确性，验证输出的 `sel` 和 `a_g` 是否符合预期。