三中取二VHDL语言编写

下面是三中取二的VHDL语言代码：

library ieee;
use ieee.std_logic_1164.all;

entity three_to_two is
    port (
        a, b, c: in std_logic;
        y1, y2: out std_logic
    );
end entity;

architecture behavioral of three_to_two is
begin
    y1 <= (a and not b) or (a and not c) or (b and not c);
    y2 <= (not a and b) or (not a and c) or (not b and c);
end architecture;

以上代码实现了三个输入信号a, b, c，以及两个输出信号y1, y2。y1的取值为a和b的逻辑与非c的逻辑与，或者a和c的逻辑与非b的逻辑与，或者b和c的逻辑与非a的逻辑与；y2的取值为a的非逻辑与b的逻辑与、a的非逻辑与c的逻辑与，或者b的非逻辑与c的逻辑与。