得益于制造工艺发展，当前的技术允许设计者在非常小的尺寸上集成数十亿晶体管来构造复杂的系统芯片。同步电路由于复杂的时钟网络在性能提升和功耗缩减方面都面临严重瓶颈。异步电路作为一种高性能低功耗的替代方法正在获得发展势头，一些工作也提出了专用的设计流程。但是这种针对纯异步电路的设计流程一方面给传统设计人员在电路设计层面带来很大的挑战。况且这种设计方法无法复用已有的同步电路，对于快速把统芯片推向市场极为不利。本文提出了创新的设计流程，首先，设计者把异步接口通路插入到同步描述的RTL将电路转换成GALS。其次，设计者对各个局部同步模块和各个异步接口通路设置时钟约束。最后，设计者基于传统EDA流程完成综合及物理设计并对所有约束进行检验。NoC在 GF22纳米 CMOS 工艺中实现，以验证所提出的设计流程。 转换后的 GALS 显示出优越的功率、性能和面积结果。整个设计流程花费的时间也明显减少。 上述这段话帮我翻译成英文。

Due to the development of manufacturing technology, current technology allows designers to integrate billions of transistors on very small dimensions to construct complex system chips. Synchronous circuits are facing serious bottlenecks in performance improvement and power reduction due to complex clock networks. As a high-performance and low-power alternative, asynchronous circuits are gaining momentum, and some works have proposed specialized design flows. However, this design method for pure asynchronous circuits poses great challenges to traditional design engineers at the circuit design level, and this design method cannot reuse existing synchronous circuits, which is extremely unfavorable for quickly bringing system chips to the market. This paper proposes an innovative design flow. Firstly, the designer inserts asynchronous interface paths into the RTL that describes synchronous circuits to convert the circuit into GALS. Secondly, the designer sets clock constraints for each local synchronous module and each asynchronous interface path. Finally, the designer completes synthesis and physical design based on traditional EDA flows and verifies all constraints. NoC is implemented in GF22 nanometer CMOS process to validate the proposed design flow. The converted GALS shows superior power, performance, and area results. The total design time has also significantly decreased.