fpga led双闪代码

以下是一个基于Verilog的FPGA LED双闪代码的示例：

module LED_Flash(
    input clk, // 时钟信号
    input rst, // 复位信号
    input button, // 按钮信号
    output reg led // LED输出信号
);

// 定义状态机状态
parameter S_IDLE = 2'b00; // 空闲状态
parameter S_SINGLE_FLASH = 2'b01; // 单闪状态
parameter S_DOUBLE_FLASH = 2'b10; // 双闪状态
parameter S_ALL_ON = 2'b11; // 全亮状态

// 定义状态机状态转移条件
parameter C_IDLE_TO_SINGLE_FLASH = 2'b00; // 从空闲状态转换到单闪状态
parameter C_SINGLE_FLASH_TO_DOUBLE_FLASH = 2'b01; // 从单闪状态转换到双闪状态
parameter C_DOUBLE_FLASH_TO_ALL_ON = 2'b10; // 从双闪状态转换到全亮状态
parameter C_ALL_ON_TO_SINGLE_FLASH = 2'b11; // 从全亮状态转换到单闪状态

// 定义状态机状态转移表
reg [1:0] state, next_state;
always @ (posedge clk or posedge rst) begin
    if (rst) begin
        state <= S_IDLE;
    end else begin
        state <= next_state;
    end
end

// 定义状态机状态转移逻辑
always @ (*) begin
    case (state)
        S_IDLE: begin
            if (button) begin
                next_state = S_SINGLE_FLASH;
            end else begin
                next_state = S_IDLE;
            end
        end
        S_SINGLE_FLASH: begin
            if (button) begin
                next_state = S_DOUBLE_FLASH;
            end else begin
                next_state = S_ALL_ON;
            end
        end
        S_DOUBLE_FLASH: begin
            if (button) begin
                next_state = S_ALL_ON;
            end else begin
                next_state = S_SINGLE_FLASH;
            end
        end
        S_ALL_ON: begin
            if (button) begin
                next_state = S_SINGLE_FLASH;
            end else begin
                next_state = S_IDLE;
            end
        end
        default: begin
            next_state = S_IDLE;
        end
    endcase
end

// 定义LED输出逻辑
always @ (posedge clk or posedge rst) begin
    if (rst) begin
        led <= 1'b0;
    end else begin
        case (state)
            S_IDLE: begin
                led <= 1'b0;
            end
            S_SINGLE_FLASH: begin
                led <= ~led;
            end
            S_DOUBLE_FLASH: begin
                led <= {2{~led}};
            end
            S_ALL_ON: begin
                led <= 1'b1;
            end
            default: begin
                led <= 1'b0;
            end
        endcase
    end
end

endmodule