linux内核中armv7初始化L2 cache的代码在哪里，是哪些

在 Linux 内核中，ARMv7 初始化 L2 cache 的代码主要位于 `arch/arm/mm/cache-v7.S` 文件中。

具体来说，以下是该文件中初始化 L2 cache 的代码：

#ifdef CONFIG_PL310_ERRATA_769419
    /* Workaround erratum 769419 in the PL310 cache controller */
    mrc     p15, 1, r0, c9, c0, 2   @ read Auxiliary Control Register
    orr     r0, r0, #(1 << 6)       @ set bit 6 (enable implicit clean/inv)
    mcr     p15, 1, r0, c9, c0, 2   @ write Auxiliary Control Register
#endif

    /*
     * Configure L2 cache controller.
     */
    mrc     p15, 1, r0, c9, c0, 2   @ read Auxiliary Control Register
    bic     r0, r0, #(0x3 << 6)     @ clear bits [7:6] (inner cache policy)
    orr     r0, r0, #(0x2 << 6)     @ write-thru, allocate on write
                                    @ for inner cache
    bic     r0, r0, #(0x3 << 4)     @ clear bits [5:4] (outer cache policy)
    orr     r0, r0, #(0x2 << 4)     @ write-thru, allocate on write
                                    @ for outer cache
    mcr     p15, 1, r0, c9, c0, 2   @ write Auxiliary Control Register

    mov     r0, #0
    mcr     p15, 2, r0, c9, c0, 1   @ disable L2 prefetch
    mcr     p15, 2, r0, c9, c0, 0   @ disable L2 cache

    mrc     p15, 1, r0, c0, c0, 1   @ Read CLIDR
    bic     r1, r0, #0x7000000      @ r1 = LoC (Line of Coherency)
    mov     r2, #0
1:  add     r3, r1, r2             @ r3 = Waypointers
    mcr     p15, 2, r3, c0, c0, 0   @ Write Waypointer
    add     r2, r2, #4
    cmp     r2, #0x100              @ 4 * 64
    blt     1b

    mov     r0, #0x200000
    mcr     p15, 2, r0, c0, c0, 2   @ Write L2 Control Register (enable L2 cache)

这段代码中，首先根据配置选项和处理器的 errata 对 L2 cache 进行一些设置（如清除某些位、设置写策略等），然后禁用 L2 的预取和缓存，接着通过读取 CLIDR 寄存器确定 L2 缓存的大小和关联性，最后启用 L2 cache。