Draw a schematic of NAND ROM with 8-word × 2-bit This ROM works as a lookup table to implement a full adder.

Here is a schematic of a NAND ROM with 8-word × 2-bit that works as a lookup table to implement a full adder:

        A1   A0
       ┌───┬───┬───┐
    D0 │ 0 │ 0 │ 1 │
       ├───┼───┼───┤
    D1 │ 0 │ 1 │ 0 │
       ├───┼───┼───┤
    D2 │ 0 │ 1 │ 1 │
       ├───┼───┼───┤
    D3 │ 1 │ 0 │ 0 │
       ├───┼───┼───┤
    D4 │ 1 │ 0 │ 1 │
       ├───┼───┼───┤
    D5 │ 1 │ 1 │ 0 │
       ├───┼───┼───┤
    D6 │ 1 │ 1 │ 1 │
       └───┴───┴───┘

This ROM has two address inputs, A1 and A0, and eight data outputs, D0 through D7. The data outputs represent the output of a full adder for each possible combination of the two input bits (A1 and A0). For example, if A1=0 and A0=1, the output of the full adder can be read from D2, which has a value of 011 (binary) or 3 (decimal). The other data outputs represent the output of the full adder for the other possible combinations of A1 and A0.