帮我用vhdl写一个101序列检测器，以及它的testbench

好的，我可以帮你用 VHDL 语言编写一个 101 序列检测器，并编写其测试台。以下是代码示例：

-- 101 sequence detector in VHDL
library ieee;
use ieee.std_logic_1164.all;

entity SeqDetect101 is
    port (
        clk : in std_logic;
        rst : in std_logic;
        din : in std_logic;
        detect : out std_logic
    );
end entity;

architecture Behavioral of SeqDetect101 is
    type state_type is (S0, S1, S2, S3);
    signal state : state_type;
begin
    process (clk, rst)
    begin
        if rst = '1' then   -- reset state machine
            state <= S0;
        elsif rising_edge(clk) then
            case state is
                when S0 =>
                    if din = '1' then
                        state <= S1;
                    else
                        state <= S0;
                    end if;
                when S1 =>
                    if din = '0' then
                        state <= S2;
                    else
                        state <= S1;
                    end if;
                when S2 =>
                    if din = '1' then
                        state <= S3;
                    else
                        state <= S0;
                    end if;
                when S3 =>
                    state <= S0;
            end case;
        end if;
    end process;

    detect <= '1' when state = S3 else '0';          -- output 1 when sequence detected
end Behavioral;


-- Testbench for 101 sequence detector
library ieee;
use ieee.std_logic_1164.all;

entity SeqDetect101_tb is
end entity;

architecture Behavioral of SeqDetect101_tb is
    signal clk, rst, din, detect : std_logic;
begin
    uut : entity work.SeqDetect101
        port map (
            clk => clk,
            rst => rst,
            din => din,
            detect => detect
        );

    process
    begin
        clk <= '0';
        rst <= '1';
        din <= '0';
        wait for 10 ns;

        rst <= '0';
        wait for 5 ns;

        din <= '1';
        wait for 5 ns;

        din <= '0';
        wait for 5 ns;

        din <= '1';
        wait for 5 ns;

        din <= '1';
        wait for 5 ns;

        din <= '0';
        wait for 5 ns;

        din <= '1';
        wait for 5 ns;

        din <= '0';   -- Sequence detected here
        wait for 5 ns;

        din <= '1';
        wait for 5 ns;

        din <= '0';
        wait for 5 ns;

        wait;
    end process;
end Behavioral;

上面的代码使用有限状态机实现 101 序列检测器。其中，输入信号为 `din`，检测到 101 序列时输出信号 `detect` 为 '1'，否则为 '0'。测试台通过输入信号 `din` 模拟输入序列，当检测到 101 序列时，输出信号 `detect` 会在对应的时钟周期输出 '1'。如果还需要其他的功能，可以在这个基础上进行修改和扩展。