verilog中统计3bit 1的个数 的设计和测试代码

以下是统计3bit 1的个数的Verilog设计和测试代码：

设计代码：

module count_3bit_ones(
input [2:0] data,
output reg count
);

always @(*) begin
case(data)
3'b001, 3'b010, 3'b100: count = 1;
3'b011, 3'b101, 3'b110: count = 2;
3'b111: count = 3;
default: count = 0;
endcase
end

endmodule

测试代码：

module count_3bit_ones_test;

reg [2:0] data;
wire count;

count_3bit_ones dut(
.data(data),
.count(count)
);

initial begin
data = 3'b000;
#10;
assert(count == 0);

data = 3'b001;
#10;
assert(count == 1);

data = 3'b010;
#10;
assert(count == 1);

data = 3'b011;
#10;
assert(count == 2);

data = 3'b100;
#10;
assert(count == 1);

data = 3'b101;
#10;
assert(count == 2);

data = 3'b110;
#10;
assert(count == 2);

data = 3'b111;
#10;
assert(count == 3);

$display("All tests passed!");
$finish;
end

endmodule