vivado实现计数器的代码和testbench程序

好的，下面是使用 VHDL 语言编写的 Vivado 计数器的代码和 testbench 程序：

计数器代码：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity counter is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           enable : in STD_LOGIC;
           count : out STD_LOGIC_VECTOR(7 downto 0));
end counter;

architecture Behavioral of counter is
    signal temp : unsigned(7 downto 0) := (others => '0');
begin
    process(clk, reset)
    begin
        if reset = '1' then
            temp <= (others => '0');
        elsif rising_edge(clk) then
            if enable = '1' then
                temp <= temp + 1;
            end if;
        end if;
    end process;
    
    count <= std_logic_vector(temp);
end Behavioral;

testbench 代码：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity counter_tb is
end counter_tb;

architecture Behavioral of counter_tb is
    constant clk_period : time := 10 ns;
    signal clk : std_logic := '0';
    signal reset : std_logic := '1';
    signal enable : std_logic := '0';
    signal count : std_logic_vector(7 downto 0);
begin
    uut : entity work.counter
        port map(clk => clk,
                 reset => reset,
                 enable => enable,
                 count => count);

    process
    begin
        reset <= '1';
        enable <= '0';
        wait for 100 ns;
        
        reset <= '0';
        enable <= '1';
        wait for 500 ns;
        
        enable <= '0';
        wait for 100 ns;
        
        enable <= '1';
        wait for 300 ns;
        
        enable <= '0';
        wait for 100 ns;
        
        enable <= '1';
        wait for 100 ns;
        
        enable <= '0';
        wait for 100 ns;
        
        enable <= '1';
        wait for 200 ns;
        
        enable <= '0';
        wait for 100 ns;
        
        wait;
    end process;

    clk_process : process
    begin
        while true loop
            clk <= not clk;
            wait for clk_period / 2;
        end loop;
    end process;
end Behavioral;

以上是使用 VHDL 语言编写的 Vivado 计数器的代码和 testbench 程序，供参考。