使用Verilog语言分别编写一个程序和其测试程序要求如下1、某赛事共有10名评委组成评委组，具有评分权限；另有1名记分员，只进行主持和记分显示；评委全部表决评分后，只有记分员按下计分按钮则总的评分才会显示在8位数码管上； 2、评委1是组长，如果该组长不同意，则8位数码管上只显示- - - - - - - -（即显示8条横杠）； 3、只有评委1（组长）投票同意后，才会将所有评委的评分进行累加，并显示在8位数码管上； 4、评委1（组长）投票记10分；评委2和评委3是两名副组长，投票记8分；其他人都是普通评委，投票记5分； 5、编写testbench仿真文件，通过波形仿真来验证正确性

好的，我可以提供一个Verilog语言的程序和相应的测试程序，实现上述要求：

// 定义模块
module evaluation_system(
  input wire clk, // 时钟信号
  input wire rst, // 复位信号
  input wire agree, // 同意信号
  input wire [9:0] scores, // 评委评分
  output wire [7:0] display // 显示评分
);

  // 定义内部信号
  reg [31:0] total_score; // 总分
  reg [7:0] final_score; // 最终评分
  reg [3:0] agree_count; // 同意票数
  reg [7:0] display_score; // 显示评分
  reg [1:0] leader_score; // 领导评分

  // 评分规则
  parameter NORMAL_SCORE = 5;
  parameter VICE_LEADER_SCORE = 8;
  parameter LEADER_SCORE = 10;

  // 初始化
  initial begin
    total_score = 0;
    final_score = 0;
    agree_count = 0;
    display_score = 0;
    leader_score = 0;
  end

  // 复位逻辑
  always @(posedge rst) begin
    total_score <= 0;
    final_score <= 0;
    agree_count <= 0;
    display_score <= 0;
    leader_score <= 0;
  end

  // 计算总分
  always @(posedge clk) begin
    if (agree) begin
      total_score <= total_score + scores;
      if (scores[0] == 1) begin
        leader_score <= LEADER_SCORE;
      end else if (scores[1] == 1 || scores[2] == 1) begin
        leader_score <= VICE_LEADER_SCORE;
      end else begin
        leader_score <= NORMAL_SCORE;
      end
    end
  end

  // 统计同意票数
  always @(posedge clk) begin
    if (agree) begin
      agree_count <= agree_count + 1;
    end
  end

  // 计算最终评分
  always @(posedge clk) begin
    if (agree_count == 10) begin
      if (scores[0] == 0) begin
        final_score <= 0;
      end else begin
        final_score <= total_score + leader_score;
      end
    end
  end

  // 显示评分
  always @(posedge clk) begin
    display_score <= final_score;
  end

  // 连接显示器
  assign display = display_score;

endmodule

接下来是测试程序：

// 定义测试程序
module evaluation_system_tb;

  // 定义内部信号
  reg clk;
  reg rst;
  reg agree;
  reg [9:0] scores;
  wire [7:0] display;

  // 实例化被测模块
  evaluation_system dut (
    .clk(clk),
    .rst(rst),
    .agree(agree),
    .scores(scores),
    .display(display)
  );

  // 初始化
  initial begin
    clk = 0;
    rst = 1;
    agree = 0;
    scores = 0;
    #10 rst = 0;
  end

  // 时钟信号
  always #5 clk = ~clk;

  // 测试用例1：评委1不同意
  initial begin
    #15 scores = 10'b0000000000;
    #5 agree = 1;
    #5 agree = 0;
    #5 agree = 1;
    #5 agree = 0;
    #5 agree = 1;
    #5 agree = 0;
    #5 agree = 1;
    #5 agree = 0;
    #5 agree = 1;
    #5 agree = 0;
    #5 agree = 1;
    #5 agree = 0;
    #5 agree = 1;
    #5 agree = 0;
    #5 $display("Test Case 1: %d", display);
    #5 assert(display == 8'b11111111) else $error("Test Case 1 failed!");
    #5 $finish;
  end

  // 测试用例2：评委1同意
  initial begin
    #15 scores = 10'b0000000001;
    #5 agree = 1;
    #5 scores = 10'b0000001000;
    #5 agree = 1;
    #5 scores = 10'b0000001000;
    #5 agree = 1;
    #5 scores = 10'b0000010101;
    #5 agree = 1;
    #5 scores = 10'b0000010101;
    #5 agree = 1;
    #5 scores = 10'b0000010101;
    #5 agree = 1;
    #5 scores = 10'b0000010101;
    #5 agree = 1;
    #5 scores = 10'b0000010101;
    #5 agree = 1;
    #5 scores = 10'b0000010101;
    #5 agree = 1;
    #5 scores = 10'b0000010101;
    #5 agree = 1;
    #5 $display("Test Case 2: %d", display);
    #5 assert(display == 8'b00010101) else $error("Test Case 2 failed!");
    #5 $finish;
  end

endmodule

以上是一个简单的评分系统的Verilog程序和测试程序，可以通过仿真来验证其正确性和稳定性。