将上面两个代码结合成一个代码并写出仿真代码

以下是将两个模块结合成一个模块的代码，并附带仿真代码：

module vlg_echo_and_cal(
    input i_clk, 
    input i_rst_n, 
    input i_clk_en, 
    input i_echo,
    output reg[13:0] o_s_mm,
    output reg[15:0] o_t_us
);

    reg[1:0] r_echo;
    wire pos_echo, neg_echo;
    reg r_cnt_en;
    reg[15:0] r_echo_cnt;
    wire[25:0] w_mult_result;
    
    mult_gen_0 uut_mult_gen_0 (
        .CLK(i_clk), 
        .A(10'd709), 
        .B(r_echo_cnt), 
        .P(w_mult_result)
    );
    
    always @(posedge i_clk) begin
        if (!i_rst_n) begin
            r_echo <= 'b0;
            r_cnt_en <= 'b0;
            r_echo_cnt <= 'b0;
            o_t_us <= 'b0;
            o_s_mm <= 'b0;
        end
        else begin
            r_echo <= {r_echo[0], i_echo};
            if (pos_echo) begin
                r_cnt_en <= 'b1;
            end
            else if (neg_echo) begin
                r_cnt_en <= 'b0;
                o_t_us <= r_echo_cnt;
            end
            else begin
                // do nothing
            end
            
            if (!r_cnt_en) begin
                r_echo_cnt <= 'b0;
            end
            else if (i_clk_en) begin
                r_echo_cnt <= r_echo_cnt + 1;
            end
            else begin
                // do nothing
            end
            
            o_s_mm <= w_mult_result[25:12];
        end
    end
    
    assign pos_echo = r_echo[0] & ~r_echo[1];
    assign neg_echo = ~r_echo[0] & r_echo[1];

endmodule

module tb_vlg_echo_and_cal;
    
    reg i_clk;
    reg i_rst_n;
    reg i_clk_en;
    reg i_echo;
    wire[13:0] o_s_mm;
    wire[15:0] o_t_us;
    
    vlg_echo_and_cal uut_vlg_echo_and_cal (
        .i_clk(i_clk),
        .i_rst_n(i_rst_n),
        .i_clk_en(i_clk_en),
        .i_echo(i_echo),
        .o_s_mm(o_s_mm),
        .o_t_us(o_t_us)
    );
    
    initial begin
        i_clk = 0;
        i_rst_n = 0;
        i_clk_en = 0;
        i_echo = 0;
        #10 i_rst_n = 1;
        #10 i_echo = 1;
        #10 i_echo = 0;
        #10 i_clk_en = 1;
        #100 $finish;
    end
    
    always #5 i_clk = ~i_clk;
    
endmodule

仿真代码：

`timescale 1ns / 1ps

module tb_vlg_echo_and_cal;
    
    reg i_clk;
    reg i_rst_n;
    reg i_clk_en;
    reg i_echo;
    wire[13:0] o_s_mm;
    wire[15:0] o_t_us;
    
    vlg_echo_and_cal uut_vlg_echo_and_cal (
        .i_clk(i_clk),
        .i_rst_n(i_rst_n),
        .i_clk_en(i_clk_en),
        .i_echo(i_echo),
        .o_s_mm(o_s_mm),
        .o_t_us(o_t_us)
    );
    
    initial begin
        i_clk = 0;
        i_rst_n = 0;
        i_clk_en = 0;
        i_echo = 0;
        #10 i_rst_n = 1;
        #10 i_echo = 1;
        #10 i_echo = 0;
        #10 i_clk_en = 1;
        #100 $finish;
    end
    
    always #5 i_clk = ~i_clk;
    
endmodule