Create a set of counters suitable for use as a 12-hour clock (with am/pm indicator). Your counters are clocked by a fast-running clk, with a pulse on ena whenever your clock should increment (i.e., once per second). reset resets the clock to 12:00 AM. pm is 0 for AM and 1 for PM. hh, mm, and ss are two BCD (Binary-Coded Decimal) digits each for hours (01-12), minutes (00-59), and seconds (00-59). Reset has higher priority than enable, and can occur even when not enabled. The following timing diagram shows the rollover behaviour from 11:59:59 AM to 12:00:00 PM and the synchronous reset and enable behaviour.

以下是一个简单的 Verilog 12 小时制时钟计数器的示例代码：

module clock12(
  input clk,
  input reset,
  input ena,
  output reg [1:0] hh,
  output reg [1:0] mm,
  output reg [1:0] ss,
  output reg pm
);

reg [5:0] count;
reg [3:0] am_pm;

always @(posedge clk) begin
  if (reset) begin
    count <= 0;
    am_pm <= 0;
  end else if (ena) begin
    count <= count + 1;
    if (count == 719) begin // 12 hours * 60 minutes / 5 seconds = 720
      count <= 0;
      am_pm <= ~am_pm;
    end
  end
end

assign pm = am_pm;
assign hh = {count[5:4], count[3:2]};
assign mm = {count[1:0], 4'b0};
assign ss = {count[1:0], 4'b0};

endmodule

这个计数器可以在每个时钟上升沿检查 ena 信号是否为高电平，如果是则增加计数器。当计数器达到 719 时，表示经过了 12 小时，计数器会回滚到 0 并翻转 am_pm 信号。输出分别是小时、分钟和秒的两个 BCD 数字，以及 am_pm 信号，0 表示 AM，1 表示 PM。你可以根据需要调整输出位宽和计数器的大小。