用vivado2020.1版本完成9人表决电路设计,LED灯表示通过、否决。要求 (1)拨码开关表示赞成与否,1~9编号(1赞成,0否决); (2)LED显示表决的结果; (3)数码管分别显示赞成、否决的人数; (4)有清零功能。 写出源代码和相应的仿真代码
时间: 2024-01-19 20:04:48 浏览: 29
以下是基于Verilog语言的9人表决电路设计的源代码和仿真代码。
源代码:
```verilog
module voting_system(
input wire clk,
input wire rst,
input wire [8:1] vote_switches,
output wire [8:1] vote_leds,
output wire [3:0] vote_count
);
// 定义投票状态
parameter IDLE = 2'b00;
parameter VOTING = 2'b01;
parameter COUNTING = 2'b10;
// 定义投票人数和赞成票数的计数器
reg [3:0] yes_count = 0;
reg [3:0] vote_count_reg = 0;
reg [3:0] vote_count_tmp = 0;
// 定义当前状态和清零信号
reg [1:0] state = IDLE;
reg clear = 0;
always @(posedge clk, posedge rst) begin
if (rst) begin
state <= IDLE;
yes_count <= 0;
vote_count_reg <= 0;
vote_count_tmp <= 0;
end else begin
case (state)
IDLE: begin
vote_count_reg <= 0;
vote_count_tmp <= 0;
vote_leds <= 9'b0;
vote_count <= 4'b0;
if (clear) begin
yes_count <= 0;
end else begin
yes_count <= 4'b0;
end
if (vote_switches != 0) begin
state <= VOTING;
end
end
VOTING: begin
vote_count_reg <= vote_count_tmp;
vote_count_tmp <= 0;
vote_leds <= vote_switches;
if (vote_switches == 9'b111111111) begin
yes_count <= yes_count + 1;
end
if (yes_count >= 5) begin
state <= COUNTING;
end
end
COUNTING: begin
vote_leds <= 9'b0;
vote_count <= vote_count_reg;
if (clear) begin
state <= IDLE;
end else begin
state <= VOTING;
end
end
endcase
end
end
// 计算赞成票数和否决票数
assign vote_count[0] = yes_count;
assign vote_count[1] = 9 - yes_count;
// 处理清零信号
always @(posedge clk) begin
if (clear) begin
vote_count_reg <= 0;
vote_count_tmp <= 0;
vote_leds <= 9'b0;
vote_count <= 4'b0;
yes_count <= 0;
state <= IDLE;
end
end
// 处理投票信号
always @(posedge clk) begin
if (state == VOTING) begin
vote_count_tmp <= vote_count_tmp + 1;
end
end
endmodule
```
仿真代码:
```verilog
module voting_system_tb;
reg clk = 0;
reg rst = 0;
reg [8:1] vote_switches = 0;
wire [8:1] vote_leds = 0;
wire [3:0] vote_count = 0;
voting_system dut (
.clk(clk),
.rst(rst),
.vote_switches(vote_switches),
.vote_leds(vote_leds),
.vote_count(vote_count)
);
always #5 clk = ~clk;
initial begin
// 初始化
rst = 1;
#10 rst = 0;
// 第一轮投票,结果应该为否决
vote_switches = 9'b000000001;
#100;
vote_switches = 9'b000000010;
#100;
vote_switches = 9'b000000011;
#100;
vote_switches = 9'b000000100;
#100;
vote_switches = 9'b000000101;
#100;
vote_switches = 9'b000000111;
#100;
vote_switches = 9'b000001111;
#100;
vote_switches = 9'b000011111;
#100;
vote_switches = 9'b000111111;
#100;
assert (vote_leds == 9'b000000000);
// 第二轮投票,结果应该为通过
vote_switches = 9'b000000001;
#100;
vote_switches = 9'b000000010;
#100;
vote_switches = 9'b000000011;
#100;
vote_switches = 9'b000000100;
#100;
vote_switches = 9'b000000101;
#100;
vote_switches = 9'b000000111;
#100;
vote_switches = 9'b000001111;
#100;
vote_switches = 9'b000011111;
#100;
vote_switches = 9'b000111110;
#100;
assert (vote_leds == 9'b111111111);
// 清零
clear = 1;
#10 clear = 0;
assert (vote_leds == 9'b000000000);
assert (vote_count == 4'b0000);
$finish;
end
endmodule
```