[DRC NSTD-1] Unspecified I/O Standard: 4 out of 4 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: row[3:0].分析报错

这是一个关于 FPGA 设计的报错信息，指出了该设计中有 4 个逻辑端口使用了默认的 I/O 标准，没有指定特定的值。这可能会导致 I/O 冲突，与板子电源或连通性不兼容，影响性能和信号完整性，甚至在极端情况下可能会损坏设备或连接的元件。要纠正这个问题，需要指定所有的 I/O 标准。如果允许未指定 I/O 标准值（不推荐），可以使用命令“set_property SEVERITY {Warning} [get_drc_checks NSTD-1]”生成比特流。报错信息指出了问题的端口是“row[3:0]”，需要在设计中指定这些端口的具体的 I/O 标准值。

相关问题

[DRC NSTD-1] Unspecified I/O Standard: 2 out of 25 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: NAND_RE_N_0, and NAND_RE_N_c_0.

这是 Vivado 在实施设计时发出的警告信息。它表示有两个逻辑端口（NAND_RE_N_0 和 NAND_RE_N_c_0）没有指定 I/O 标准，而是使用了默认值。这可能会引起 I/O 冲突或与板子电源或连接性不兼容，影响性能、信号完整性，甚至可能导致损坏。为了解决这个问题，需要为所有逻辑端口指定 I/O 标准。如果允许使用未指定 I/O 标准值的设计位流（不推荐），可以使用该命令：set_property SEVERITY {Warning} [get_drc_checks NSTD-1]。在 Vivado Runs 基础设施中使用时，在写入位流步骤的前钩子中添加这个命令。

[DRC NSTD-1] Unspecified I/O Standard: 9 out of 139 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: USBIND_0_0_port_indctl[1:0], USBIND_0_0_vbus_pwrfault, USBIND_0_0_vbus_pwrselect, UART_0_0_rxd, UART_0_0_txd, FCLK_RESET0_N_0, FCLK_CLK0_0, and GPIO_tri_io[0].

这是来自 Vivado 的警告信息，提示设计中有一些逻辑端口使用了默认的 I/O 标准值，而没有指定用户定义的特定值。这可能会导致性能、信号完整性或甚至设备或组件损坏的问题。为了解决这个问题，你需要为设计中的所有逻辑端口指定特定的 I/O 标准。如果你选择忽略此警告，你仍然可以生成位流，但不推荐这样做。要这样做，可以使用命令 "set_property SEVERITY {Warning} [get_drc_checks NSTD-1]" 将其添加到 .tcl 文件中，并将该文件作为实现运行的 write_bitstream 步骤的预钩子。消息中列出的问题端口包括 USBIND_0_0_port_indctl[1:0]、USBIND_0_0_vbus_pwrfault、USBIND_0_0_vbus_pwrselect、UART_0_0_rxd、UART_0_0_txd、FCLK_RESET0_N_0、FCLK_CLK0_0 和 GPIO_tri_io[0]。