帮我用Verilog设计一个输入像素数据为16位二进制数的96*96图像数据流，深度为453，且每个时钟周期内可以同时输出第0、1、2、225、226、227、450、451、452位寄存器中的数据的移位寄存器模块

module shift_reg(
input clk, //时钟信号
input [15:0] data_in, //输入数据
input [2:0] select, //选择寄存器
output [15:0] data_out //输出数据
);

reg [15:0] reg0, reg1, reg2, reg225, reg226, reg227, reg450, reg451, reg452;

always @(posedge clk) begin
case (select)
3'b000: reg0 <= data_in;
3'b001: reg1 <= data_in;
3'b010: reg2 <= data_in;
3'b011: reg225 <= data_in;
3'b100: reg226 <= data_in;
3'b101: reg227 <= data_in;
3'b110: reg450 <= data_in;
3'b111: reg451 <= data_in;
3'b111: reg452 <= data_in;
endcase
end

always @(posedge clk) begin
case (select)
3'b000: data_out <= reg0;
3'b001: data_out <= reg1;
3'b010: data_out <= reg2;
3'b011: data_out <= reg225;
3'b100: data_out <= reg226;
3'b101: data_out <= reg227;
3'b110: data_out <= reg450;
3'b111: data_out <= reg451;
3'b111: data_out <= reg452;
endcase
end

endmodule

module image_data(
input clk, //时钟信号
input [15:0] pixel_in, //输入像素数据
output [15:0] pixel_out //输出像素数据
);

reg [2:0] select = 3'b000; //初始选择第0个寄存器

shift_reg reg0(.clk(clk), .data_in(pixel_in), .select(3'b000), .data_out(pixel_out0));
shift_reg reg1(.clk(clk), .data_in(pixel_in), .select(3'b001), .data_out(pixel_out1));
shift_reg reg2(.clk(clk), .data_in(pixel_in), .select(3'b010), .data_out(pixel_out2));
shift_reg reg225(.clk(clk), .data_in(pixel_in), .select(3'b011), .data_out(pixel_out225));
shift_reg reg226(.clk(clk), .data_in(pixel_in), .select(3'b100), .data_out(pixel_out226));
shift_reg reg227(.clk(clk), .data_in(pixel_in), .select(3'b101), .data_out(pixel_out227));
shift_reg reg450(.clk(clk), .data_in(pixel_in), .select(3'b110), .data_out(pixel_out450));
shift_reg reg451(.clk(clk), .data_in(pixel_in), .select(3'b111), .data_out(pixel_out451));
shift_reg reg452(.clk(clk), .data_in(pixel_in), .select(3'b111), .data_out(pixel_out452));

always @(posedge clk) begin
select <= select + 1;
if (select == 3'b111) select <= 3'b000; //循环选择寄存器
end

always @(posedge clk) begin
case (select)
3'b000: pixel_out <= pixel_out0;
3'b001: pixel_out <= pixel_out1;
3'b010: pixel_out <= pixel_out2;
3'b011: pixel_out <= pixel_out225;
3'b100: pixel_out <= pixel_out226;
3'b101: pixel_out <= pixel_out227;
3'b110: pixel_out <= pixel_out450;
3'b111: pixel_out <= pixel_out451;
3'b111: pixel_out <= pixel_out452;
endcase
end

endmodule