// SYS_CLK_FREQ表示输入时钟频率；TARGET_CLK_FREQ表示目标时钟频率；N表示计数器的位宽 module clkdiv #(parameter SYS_CLK_FREQ = 100_000_000, TARGET_CLK_FREQ = 10_000_000, N = 3)( input sys_clk, input sys_rst_n, output clk_out ); // 请在下面添加代码，对输入时钟（100MHz）进行10分频 // 代码量预计10~13行 /****** Begin / / End ******/ endmodule输入信号： 时钟周期为10ns（100MHz）； 0ns: sys_clk = 0, sys_rst_n = 0； 20ns: sys_rst_n = 1； 复位信号无效后，再经历20个时钟上升沿。 预期输出： VCD info: dumpfile waveform.vcd opened for output. At time 0ns: sys_rst_n = 0, clk_out = x At time 5ns: sys_rst_n = 0, clk_out = 0 At time 20ns: sys_rst_n = 1, clk_out = 0 At time 65ns: sys_rst_n = 1, clk_out = 1 At time 115ns: sys_rst_n = 1, clk_out = 0 At time 165ns: sys_rst_n = 1, clk_out = 1 At time 215ns: sys_rst_n = 1, clk_out = 0

module clkdiv #(parameter SYS_CLK_FREQ = 100_000_000, TARGET_CLK_FREQ = 10_000_000, N = 3)(
input sys_clk,
input sys_rst_n,
output clk_out
);

reg [N-1:0] counter;
reg clk_out_reg;

always @(posedge sys_clk or negedge sys_rst_n) begin
if (~sys_rst_n) begin
counter <= 0;
clk_out_reg <= 0;
end else begin
counter <= counter + 1;
if (counter == SYS_CLK_FREQ / TARGET_CLK_FREQ / 2 - 1) begin
counter <= 0;
clk_out_reg <= ~clk_out_reg;
end
end
end

assign clk_out = clk_out_reg;

endmodule