用Verlog代码写一个Mealy型状态机，要求能设计一个可以识别“01101”的序列检测电路并编写测试文件testbench.v 文件进行仿真

下面是一个基于Verilog的Mealy型状态机，可以识别“01101”的序列检测电路。同时，我也编写了一个简单的testbench.v文件进行仿真测试。

module sequence_detector(
    input clk, //时钟输入
    input rst, //同步复位输入
    input in,  //序列输入
    output reg out //检测结果输出
);

//定义状态枚举类型
typedef enum logic [1:0] {
    s0,
    s1,
    s2,
    s3,
    s4
} state_type;

//定义状态寄存器和状态转移逻辑
reg [1:0] state, next_state;
always @ (posedge clk, posedge rst) begin
    if (rst) begin
        state <= s0;
    end
    else begin
        state <= next_state;
    end
end

//定义状态转移逻辑
always @ (*) begin
    case (state)
        s0: begin
            if (in == 0) begin
                next_state = s0;
            end
            else begin
                next_state = s1;
            end
        end
        s1: begin
            if (in == 0) begin
                next_state = s0;
            end
            else begin
                next_state = s2;
            end
        end
        s2: begin
            if (in == 1) begin
                next_state = s3;
            end
            else begin
                next_state = s0;
            end
        end
        s3: begin
            if (in == 0) begin
                next_state = s4;
            end
            else begin
                next_state = s0;
            end
        end
        s4: begin
            if (in == 1) begin
                next_state = s3;
            end
            else begin
                next_state = s0;
            end
        end
        default: next_state = s0;
    endcase
end

//定义输出逻辑
always @ (state) begin
    if (state == s4) begin
        out = 1;
    end
    else begin
        out = 0;
    end
end

endmodule

下面是testbench.v文件，用于对状态机进行仿真测试。

module testbench();

//定义时钟和复位信号
reg clk, rst;

//定义输入信号和输出信号
reg in;
wire out;

//实例化状态机
sequence_detector dut(
    .clk(clk),
    .rst(rst),
    .in(in),
    .out(out)
);

//定义仿真时钟
initial begin
    clk = 0;
    forever #10 clk = ~clk;
end

//定义复位信号
initial begin
    rst = 1;
    #20 rst = 0;
end

//定义输入信号
initial begin
    in = 0;
    #30 in = 1;
    #10 in = 1;
    #10 in = 0;
    #10 in = 1;
    #10 in = 0;
    #20 $finish;
end

//定义输出结果
always @ (posedge clk) begin
    $display("out=%b", out);
end

endmodule