8位跑马灯 verilog

module eight_bit_marquee(
input clk,
input reset,
input [7:0] data_in,
output [7:0] data_out
);

reg [7:0] shift_reg;
reg [2:0] count;

always @(posedge clk) begin
if (reset) begin
shift_reg <= 8'b00000000;
count <= 3'b000;
end
else begin
count <= count + 1;
case(count)
3'b000: shift_reg <= data_in;
3'b001: shift_reg <= {shift_reg[6:0], shift_reg[7]};
3'b010: shift_reg <= {shift_reg[5:0], shift_reg[7:6]};
3'b011: shift_reg <= {shift_reg[4:0], shift_reg[7:5]};
3'b100: shift_reg <= {shift_reg[3:0], shift_reg[7:4]};
3'b101: shift_reg <= {shift_reg[2:0], shift_reg[7:3]};
3'b110: shift_reg <= {shift_reg[1:0], shift_reg[7:2]};
3'b111: shift_reg <= {shift_reg[0], shift_reg[7:1]};
endcase
end
end

assign data_out = shift_reg;

endmodule