用Verilog语句分别写出1位和8位加法器的Verilog代码和测试文件

1位加法器的Verilog代码：

module one_bit_adder(
    input a,
    input b,
    input cin,
    output sum,
    output cout
    );
    assign sum = a ^ b ^ cin;
    assign cout = (a & b) | (a & cin) | (b & cin);
endmodule

1位加法器的测试文件：

module tb_one_bit_adder;

    reg a, b, cin;
    wire sum, cout;

    one_bit_adder oba(
        .a(a),
        .b(b),
        .cin(cin),
        .sum(sum),
        .cout(cout)
    );

    initial begin
        a = 1'b0;
        b = 1'b0;
        cin = 1'b0;
        #10 $display("a=%b, b=%b, cin=%b, sum=%b, cout=%b", a, b, cin, sum, cout);

        a = 1'b0;
        b = 1'b1;
        cin = 1'b0;
        #10 $display("a=%b, b=%b, cin=%b, sum=%b, cout=%b", a, b, cin, sum, cout);

        a = 1'b1;
        b = 1'b0;
        cin = 1'b0;
        #10 $display("a=%b, b=%b, cin=%b, sum=%b, cout=%b", a, b, cin, sum, cout);

        a = 1'b1;
        b = 1'b1;
        cin = 1'b0;
        #10 $display("a=%b, b=%b, cin=%b, sum=%b, cout=%b", a, b, cin, sum, cout);

        a = 1'b0;
        b = 1'b0;
        cin = 1'b1;
        #10 $display("a=%b, b=%b, cin=%b, sum=%b, cout=%b", a, b, cin, sum, cout);

        a = 1'b0;
        b = 1'b1;
        cin = 1'b1;
        #10 $display("a=%b, b=%b, cin=%b, sum=%b, cout=%b", a, b, cin, sum, cout);

        a = 1'b1;
        b = 1'b0;
        cin = 1'b1;
        #10 $display("a=%b, b=%b, cin=%b, sum=%b, cout=%b", a, b, cin, sum, cout);

        a = 1'b1;
        b = 1'b1;
        cin = 1'b1;
        #10 $display("a=%b, b=%b, cin=%b, sum=%b, cout=%b", a, b, cin, sum, cout);

        $finish;
    end

endmodule

8位加法器的Verilog代码：

module eight_bit_adder(
    input [7:0] a,
    input [7:0] b,
    input cin,
    output [7:0] sum,
    output cout
    );
    wire [7:0] carry;
    one_bit_adder oba0(
        .a(a[0]),
        .b(b[0]),
        .cin(cin),
        .sum(sum[0]),
        .cout(carry[0])
    );
    one_bit_adder oba1(
        .a(a[1]),
        .b(b[1]),
        .cin(carry[0]),
        .sum(sum[1]),
        .cout(carry[1])
    );
    one_bit_adder oba2(
        .a(a[2]),
        .b(b[2]),
        .cin(carry[1]),
        .sum(sum[2]),
        .cout(carry[2])
    );
    one_bit_adder oba3(
        .a(a[3]),
        .b(b[3]),
        .cin(carry[2]),
        .sum(sum[3]),
        .cout(carry[3])
    );
    one_bit_adder oba4(
        .a(a[4]),
        .b(b[4]),
        .cin(carry[3]),
        .sum(sum[4]),
        .cout(carry[4])
    );
    one_bit_adder oba5(
        .a(a[5]),
        .b(b[5]),
        .cin(carry[4]),
        .sum(sum[5]),
        .cout(carry[5])
    );
    one_bit_adder oba6(
        .a(a[6]),
        .b(b[6]),
        .cin(carry[5]),
        .sum(sum[6]),
        .cout(carry[6])
    );
    one_bit_adder oba7(
        .a(a[7]),
        .b(b[7]),
        .cin(carry[6]),
        .sum(sum[7]),
        .cout(cout)
    );
endmodule

8位加法器的测试文件：

module tb_eight_bit_adder;

    reg [7:0] a, b;
    reg cin;
    wire [7:0] sum;
    wire cout;

    eight_bit_adder eba(
        .a(a),
        .b(b),
        .cin(cin),
        .sum(sum),
        .cout(cout)
    );

    initial begin
        a = 8'b00000000;
        b = 8'b00000000;
        cin = 1'b0;
        #10 $display("a=%b, b=%b, cin=%b, sum=%b, cout=%b", a, b, cin, sum, cout);

        a = 8'b00000001;
        b = 8'b00000001;
        cin = 1'b0;
        #10 $display("a=%b, b=%b, cin=%b, sum=%b, cout=%b", a, b, cin, sum, cout);

        a = 8'b00000001;
        b = 8'b00000001;
        cin = 1'b1;
        #10 $display("a=%b, b=%b, cin=%b, sum=%b, cout=%b", a, b, cin, sum, cout);

        a = 8'b11111111;
        b = 8'b11111111;
        cin = 1'b0;
        #10 $display("a=%b, b=%b, cin=%b, sum=%b, cout=%b", a, b, cin, sum, cout);

        a = 8'b11111111;
        b = 8'b11111111;
        cin = 1'b1;
        #10 $display("a=%b, b=%b, cin=%b, sum=%b, cout=%b", a, b, cin, sum, cout);

        $finish;
    end

endmodule

以上是1位和8位加法器的Verilog代码和测试文件的示例。注意：这只是一个简单的示例，实际的电路可能需要更多的测试和调试。