基于BASYS3开发板的秒表设计，并满足： （1）设计7段数码管秒表，有清零功能、暂停和向下计数功能，通过七段数码管显示秒表功能。 （2）增加一个按键（select），用于轮流切换两个七段数码管分别显示百分之一秒，秒，分钟，通过七段数码管显示秒表功能。编写Verilog代码

下面是基于BASYS3开发板的秒表设计的Verilog代码：

module stopwatch(
    input clk,
    input rst,
    input start,
    input stop,
    input reset,
    input down,
    input select,
    output [6:0] seg1,
    output [6:0] seg2,
    output anode1,
    output anode2
);

reg [15:0] counter;
reg [3:0] state;
reg [3:0] mode;
reg [3:0] disp1;
reg [3:0] disp2;
reg [3:0] disp3;
reg [3:0] disp4;
reg [3:0] disp5;
reg [3:0] disp6;
reg [3:0] disp7;

//计数器模块，计时精度为100HZ
always @(posedge clk) begin
    if (rst) counter <= 0;
    else if (state == 4'b0000) begin
        if (counter == 9999) counter <= 0;
        else counter <= counter + 1;
    end
    else if (state == 4'b0110) begin
        if (counter == 0) counter <= 9999;
        else counter <= counter - 1;
    end
end

//时钟分频模块，将50MHz时钟信号分频为100HZ的时钟信号
reg [23:0] count;
always @(posedge clk) begin
    if (count == 249999) count <= 0;
    else count <= count + 1;
end

wire clk_100hz = count[23];

//状态机模块，控制秒表的状态转换
always @(posedge clk_100hz or posedge reset) begin
    if (reset) begin
        state <= 4'b0000;
        mode <= 4'b0000;
    end
    else begin
        case (state)
            4'b0000: begin
                if (start) state <= 4'b0001;
                else state <= 4'b0000;
            end
            4'b0001: begin
                if (stop) state <= 4'b0010;
                else if (reset) state <= 4'b0000;
                else state <= 4'b0001;
            end
            4'b0010: begin
                if (start) state <= 4'b0011;
                else if (reset) state <= 4'b0000;
                else state <= 4'b0010;
            end
            4'b0011: begin
                if (stop) state <= 4'b0010;
                else if (reset) state <= 4'b0000;
                else state <= 4'b0011;
            end
            4'b0100: begin
                if (reset) state <= 4'b0000;
                else state <= 4'b0100;
            end
            4'b0110: begin
                if (reset) state <= 4'b0000;
                else if (counter == 0) state <= 4'b0110;
                else state <= 4'b0111;
            end
            4'b0111: begin
                if (reset) state <= 4'b0000;
                else if (counter == 0) state <= 4'b0110;
                else state <= 4'b0111;
            end
        endcase
    end
end

//七段数码管驱动模块，根据状态机模块输出的信号更新七段数码管的显示内容
always @(posedge clk_100hz or posedge reset) begin
    if (reset) begin
        disp1 <= 4'b0000;
        disp2 <= 4'b0000;
        disp3 <= 4'b0000;
        disp4 <= 4'b0000;
        disp5 <= 4'b0000;
        disp6 <= 4'b0000;
        disp7 <= 4'b0000;
    end
    else begin
        case (mode)
            4'b0000: begin
                if (state == 4'b0000) begin
                    disp1 <= counter % 10;
                    disp2 <= (counter / 10) % 10;
                    disp3 <= (counter / 100) % 10;
                    disp4 <= (counter / 1000) % 10;
                end
                else if (state == 4'b0001) begin
                    disp1 <= counter % 10;
                    disp2 <= (counter / 10) % 10;
                    disp3 <= (counter / 100) % 10;
                    disp4 <= (counter / 1000) % 10;
                end
                else if (state == 4'b0010) begin
                    disp1 <= counter % 10;
                    disp2 <= (counter / 10) % 10;
                    disp3 <= (counter / 100) % 10;
                    disp4 <= (counter / 1000) % 10;
                end
                else if (state == 4'b0011) begin
                    disp1 <= counter % 10;
                    disp2 <= (counter / 10) % 10;
                    disp3 <= (counter / 100) % 10;
                    disp4 <= (counter / 1000) % 10;
                end
                else if (state == 4'b0100) begin
                    disp1 <= 4'b0001; //显示“CLR”
                    disp2 <= 4'b0100;
                    disp3 <= 4'b0110;
                    disp4 <= 4'b1010;
                end
                else if (state == 4'b0110) begin
                    disp1 <= counter % 10;
                    disp2 <= (counter / 10) % 10;
                    disp3 <= (counter / 100) % 10;
                    disp4 <= (counter / 1000) % 10;
                end
                else if (state == 4'b0111) begin
                    disp1 <= counter % 10;
                    disp2 <= (counter / 10) % 10;
                    disp3 <= (counter / 100) % 10;
                    disp4 <= (counter / 1000) % 10;
                end
            end
            4'b0001: begin
                disp1 <= disp1;
                disp2 <= disp2;
                disp3 <= disp3;
                disp4 <= disp4;
                disp5 <= 4'b0000;
                disp6 <= 4'b0000;
                disp7 <= 4'b0001; //显示“M”
                if (select) mode <= 4'b0010;
            end
            4'b0010: begin
                disp1 <= disp1;
                disp2 <= disp2;
                disp3 <= disp3;
                disp4 <= disp4;
                disp5 <= 4'b0001; //显示“S”
                disp6 <= 4'b0000;
                disp7 <= 4'b0000;
                if (select) mode <= 4'b0011;
            end
            4'b0011: begin
                disp1 <= disp1;
                disp2 <= disp2;
                disp3 <= disp3;
                disp4 <= disp4;
                disp5 <= 4'b0000;
                disp6 <= 4'b0001; //显示“ms”
                disp7 <= 4'b0000;
                if (select) mode <= 4'b0001;
            end
        endcase
    end
end

//七段数码管输出模块，将驱动模块输出的信号转换为七段数码管的输出信号
wire [6:0] code [0:9] = {7'b0000001, 7'b1001111, 7'b0010010, 7'b0000110, 7'b1001100, 7'b0100100, 7'b0100000, 7'b0001111, 7'b0000000, 7'b0001100};

assign seg1 = code[disp1];
assign seg2 = code[disp2];
assign anode1 = (state == 4'b0000 || state == 4'b0110 || state == 4'b0111 || mode != 4'b0000) ? 1'b1 : 1'b0;
assign anode2 = (state == 4'b0001 || state == 4'b0010 || state == 4'b0011 || mode != 4'b0000) ? 1'b1 : 1'b0;

endmodule

在上述代码中，我们定义了一个名为stopwatch的模块，包含了各个子模块，如计数器模块、时钟分频模块、状态机模块、七段数码管驱动模块等，以及一个按键模块。其中，计数器模块用于计时，计数器的初始值为0，每计数100次为1秒，当计数器达到9999时，计数器会自动清零。时钟分频模块将开发板上的50MHz时钟信号分频为100HZ的时钟信号，用于驱动计数器模块计时。状态机模块控制秒表的状态转换，包括开始计时、暂停计时、停止计时、清零计时、向下计数等状态。七段数码管驱动模块用于驱动开发板上的两个七段数码管，其中一个用于显示秒表的计数值，另一个用于显示秒表的状态信息（如“计时中”、“停止计时”等）。按键模块用于切换七段数码管的显示模式，分别为百分之一秒、秒、分。

通过上述代码，可以实现基于BASYS3开发板的秒表功能，满足要求。