module mppcs_block_dec #( parameter DW = 32, /// max. data width parameter HW = 4, /// max. header width parameter ND = 16 /// max. number of data per block ) ( /// ingress data interface input logic [DW-1:0] data_in, /// ingress data before header extraction input logic in_valid, /// ingress flow control output logic in_ready, /// ingress flow control /// egress data interface output logic block_start, /// block synchronization output logic [HW-1:0] header_out, /// block header output logic [DW-1:0] data_out, /// egress data after header extraction output logic out_valid, /// egress flow control input logic out_ready, /// egress flow control /// control options input [$clog2(DW)-1:0] msb_data, /// number of data bits - 1 input [$clog2(HW)-1:0] msb_header, /// number of header bits - 1 input [$clog2(ND)-1:0] msb_num_data, /// number of data per block - 1 output logic sync_track, /// block sync tracking signal input logic sync_mode, /// 0: use external sync directly, 1 : use internal sync after assertion of external sync input logic [3:0] sync_offset, /// offset between sync and block start signal input logic sync_start, /// external sync input logic enable, /// 0: clock-gated, 1: mission mode input logic bypass, /// 1: data pass-through without header insertion /// clock & reset input clk, input rst );

这是一个Verilog HDL代码模块，实现了一个带有数据和头部的块解码器。它的作用是从数据流中提取出块，并将数据和头部分别输出。模块中包含了许多参数，如最大数据宽度DW、最大头部宽度HW、每个块中的最大数据数目ND等。模块的输入包括数据流、数据有效信号、流控制信号等；输出包括块同步信号、头部、数据、数据有效信号等。此外，还包括一些控制选项，如数据位数、头部位数、每个块中数据的数量等。模块还包括时钟和复位信号。

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module mppcs_block_enc #( parameter DW = 32, /// max. data width parameter HW = 4, /// max. header width parameter ND = 16 /// max. data per block ) ( /// ingress data interface input logic block_start, /// block synchronization signal input logic [HW-1:0] header_in, /// block header input logic [DW-1:0] data_in, /// ingress data before header insertion input logic in_valid, /// ingress flow control output logic in_ready, /// ingress flow control /// egress data interface output logic [DW-1:0] data_out, /// egress data after header insertion output logic out_valid, /// egress flow control input logic out_ready, /// egress flow control /// control options input [$clog2(DW)-1:0] msb_data, /// number of data bits - 1 input [$clog2(HW)-1:0] msb_header, /// number of header bits - 1 input [$clog2(ND)-1:0] msb_num_data, /// number of data per block - 1 output logic sync_track, /// block synchronization tracking signal input logic sync_mode, /// 0: use block_start, 1: use sync_track input logic enable, /// 0: clock-gated, 1: mission mode input logic bypass, /// 1: data pass-through without header insertion /// clock & reset input clk, input rst );

这段代码中的参数 DW、HW 和 ND 分别代表数据的最大宽度、头部的最大宽度和每个块中数据的最大数量。模块包含 ingress 和 egress 数据接口，其中 ingress 数据接口包括了用于同步块的 block_start 信号、块头部的 header_in 信号、未插入头部的 ingress 数据 data_in 信号、ingress 控制信号 in_valid 和 in_ready。egress 数据接口包括了插入头部后的 egress 数据 data_out 信号、egress 控制信号 out_valid 和 out_ready。控制选项包括了数据位数 msb_data、头部位数 msb_header、每块数据的数量 msb_num_data 和同步跟踪信号 sync_track。同时，还包括了使能和绕过选项 enable 和 bypass，以及时钟和复位输入 clk 和 rst。

/// programmable block decoder to support protocols such as 64b66b, 64b67b, 128b130b, 128b132b module mppcs_block_dec #( parameter DW = 32, /// max. data width parameter DATA_WIDTH = 32, parameter HW = 4, /// max. header width 4 parameter ND = 16 /// max. number of data per block parameter DATA_PER_BLOCK = 64, ) ( /// ingress data interface input logic [DW-1:0] data_in, /// ingress data before header extraction input logic in_valid, /// ingress flow control output logic in_ready, /// ingress flow control /// egress data interface output logic block_start, /// block synchronization output logic [HW-1:0] header_out, /// block header output logic [DW-1:0] data_out, /// egress data after header extraction output logic out_valid, /// egress flow control input logic out_ready, /// egress flow control /// control options input [$clog2(DW)-1:0] msb_data, /// number of data bits - 1 input [$clog2(HW)-1:0] msb_header, /// number of header bits - 1 input [$clog2(ND)-1:0] msb_num_data, /// number of data per block - 1 output logic sync_track, /// block sync tracking signal input logic sync_mode, /// 0: use external sync directly, 1 : use internal sync after assertion of external sync input logic [3:0] sync_offset, /// offset between sync and block start signal input logic sync_start, /// external sync input logic enable, /// 0: clock-gated, 1: mission mode input logic bypass, /// 1: data pass-through without header insertion /// clock & reset input clk, input rst ); /// mask unused bits in header and data wire [DW+1 :0] data_msk = {({{(DW-1){1'b0}},1'b1}<<msb_data),1'b0} - 1'b1; wire [DW-1:0] data_eff = data_msk[DW-1:0] & data_in; wire [HW+1 :0] header_msk = {({{(HW-1){1'b0}},1'b1}<<msb_header),1'b0} - 1'b1; /// block synchronization wire block_sync_en = enable & ~bypass; logic [$clog2(ND)-1:0] cnt_block_data,cnt_block_data_nxt; logic sync_start_lat; always @(posedge clk or posedge rst) begin if (rst) sync_start_lat <= 0; else sync_start_lat <= sync_start; end

这段代码是一个可编程块解码器，用于支持诸如64b66b、64b67b、128b130b、128b132b等协议。该模块有一个数据输入接口，可以输入数据进行解码；同时也有一个数据输出接口，可以输出解码后的数据。在解码数据时，还需要进行数据屏蔽和头部提取等操作。另外，该模块还具备一些控制选项，比如同步跟踪信号、同步模式和使能等。最后，该模块还有时钟和复位信号。