用verilog语言写一个交通灯

的控制器的代码，包括红绿黄三个灯的状态转换和计时器的实现。

module traffic_light(
input clk,
input rst,
output reg red,
output reg yellow,
output reg green
);

parameter IDLE = 2'b00;
parameter RED = 2'b01;
parameter YELLOW = 2'b10;
parameter GREEN = 2'b11;

reg [1:0] state;
reg [22:0] timer;

always @(posedge clk) begin
if (rst) begin
state <= IDLE;
timer <= 0;
red <= 1'b0;
yellow <= 1'b0;
green <= 1'b0;
end else begin
case(state)
IDLE: begin
red <= 1'b1;
yellow <= 1'b0;
green <= 1'b0;
timer <= 10_000_000;
state <= RED;
end
RED: begin
red <= 1'b1;
yellow <= 1'b0;
green <= 1'b0;
if (timer <= 0) begin
timer <= 5_000_000;
state <= YELLOW;
end else begin
timer <= timer - 1;
state <= RED;
end
end
YELLOW: begin
red <= 1'b0;
yellow <= 1'b1;
green <= 1'b0;
if (timer <= 0) begin
timer <= 10_000_000;
state <= GREEN;
end else begin
timer <= timer - 1;
state <= YELLOW;
end
end
GREEN: begin
red <= 1'b0;
yellow <= 1'b0;
green <= 1'b1;
if (timer <= 0) begin
timer <= 5_000_000;
state <= YELLOW;
end else begin
timer <= timer - 1;
state <= GREEN;
end
end
endcase
end
end
endmodule

请注意：此代码只是一个简单的例子，并未经过验证和验证，可能会有一些错误或不足之处。如果要在实际环境中使用这个模块，请进行适当的修改和测试以确保其正确和可靠。