三线八线译码器VHDL代码

以下是一个简单的三线八线译码器的VHDL代码：

entity decoder is
    port (
        input: in std_logic_vector(2 downto 0);
        output: out std_logic_vector(7 downto 0)
    );
end entity;

architecture Behavioral of decoder is
begin
    process(input)
    begin
        case input is
            when "000" => output <= "00000001";
            when "001" => output <= "00000010";
            when "010" => output <= "00000100";
            when "011" => output <= "00001000";
            when "100" => output <= "00010000";
            when "101" => output <= "00100000";
            when "110" => output <= "01000000";
            when "111" => output <= "10000000";
            when others => output <= (others => '0');
        end case;
    end process;
end architecture;

以上代码中，输入端口为一个三位向量，输出端口为一个八位向量。case语句将根据输入的值将输出向量设置为对应的输出值。当输入值不在预期范围内时，输出向量将被设置为全零。