四位全加器verilog代码

下面是一个四位全加器的Verilog代码：

module four_bit_adder(
  input [3:0] A, B,
  input Cin,
  output [3:0] S,
  output Cout
);

  wire c1, c2, c3;

  full_adder FA0(A[0], B[0], Cin, S[0], c1);
  full_adder FA1(A[1], B[1], c1, S[1], c2);
  full_adder FA2(A[2], B[2], c2, S[2], c3);
  full_adder FA3(A[3], B[3], c3, S[3], Cout);

endmodule

module full_adder(
  input A, B, Cin,
  output S,
  output Cout
);

  wire c1, c2;

  xor(S, A, B);
  and(c1, A, B);
  and(c2, S, Cin);
  or(Cout, c1, c2);

endmodule

在这个代码中，我们使用四个全加器（`full_adder`）来实现四位全加器。每个全加器都接收两个输入（`A`和`B`）和一个进位（`Cin`），并输出一个和（`S`）和一个进位（`Cout`）。在主模块（`four_bit_adder`）中，我们将这四个全加器连接起来，以实现四位加法。

相关问题

四位全加器verilog仿真

好的，以下是四位全加器的 Verilog 代码和仿真结果：

module full_adder(
    input a,
    input b,
    input cin,
    output sum,
    output cout
);

assign sum = a ^ b ^ cin;
assign cout = (a & b) | (a & cin) | (b & cin);

endmodule

module four_bit_adder(
    input [3:0] a,
    input [3:0] b,
    input cin,
    output [3:0] sum,
    output cout
);

wire c1, c2, c3;

full_adder fa0(a[0], b[0], cin, sum[0], c1);
full_adder fa1(a[1], b[1], c1, sum[1], c2);
full_adder fa2(a[2], b[2], c2, sum[2], c3);full_adder fa3(a[3], b[3], c3, sum[3], cout);

endmodule

仿真结果如下图所示：


四位全加器verilog仿真激励

以下是四位全加器的Verilog代码和仿真激励：

module full_adder(
    input a,
    input b,
    input cin,
    output sum,
    output cout
);

assign sum = a ^ b ^ cin;
assign cout = (a & b) | (a & cin) | (b & cin);

endmodule

module four_bit_adder(
    input [3:0] a,
    input [3:0] b,
    input cin,
    output [3:0] sum,
    output cout
);

wire c1, c2, c3;

full_adder fa0(a[0], b[0], cin, sum[0], c1);
full_adder fa1(a[1], b[1], c1, sum[1], c2);
full_adder fa2(a[2], b[2], c2, sum[2], c3);
full_adder fa3(a[3], b[3], c3, sum[3], cout);

endmodule

module testbench();

reg [3:0] a;
reg [3:0] b;
reg cin;
wire [3:0] sum;
wire cout;

four_bit_adder dut(a, b, cin, sum, cout);

initial begin
    a = 4'b0000;
    b = 4'b0000;
    cin = 0;
    
    #10 a = 4'b0001; b = 4'b0001;
    #10 a = 4'b0010; b = 4'b0010;
    #10 a = 4'b0100; b = 4'b0100;
    #10 a = 4'b1000; b = 4'b1000;
    
    #10 a = 4'b1111; b = 4'b0001;
    #10 a = 4'b1111; b = 4'b0010;
    #10 a = 4'b1111; b = 4'b0100;
    #10 a = 4'b1111; b = 4'b1000;
    
    #10 a = 4'b1010; b = 4'b0101;
    #10 a = 4'b1100; b = 4'b0011;
    #10 a = 4'b1111; b = 4'b1111;
    
    #10 a = 4'b0111; b = 4'b1000;
    #10 a = 4'b0001; b = 4'b1111;
    
    #10 a = 4'b1010; b = 4'b0101; cin = 1;
    #10 a = 4'b1100; b = 4'b0011; cin = 1;
    #10 a = 4'b1111; b = 4'b1111; cin = 1;
    
    #10 a = 4'b0111; b = 4'b1000; cin = 1;
    #10 a = 4'b0001; b = 4'b1111; cin = 1;
end

endmodule

仿真结果如下：