用状态机设计一个串行序列检测器，要求具备检测串行输入为10010序列，包括代码和状态转换表

以下是用 Verilog HDL 语言实现的状态机设计：

module serial_detector(input clk, input reset, input data, output reg detect);

  parameter IDLE = 2'b00, S1 = 2'b01, S2 = 2'b10, DETECT = 2'b11;
  
  reg [1:0] state, next_state;
  
  always @(posedge clk) begin
    if (reset) begin
      state <= IDLE;
    end
    else begin
      state <= next_state;
    end
  end
  
  always @* begin
    detect = 0;
    next_state = state;
    case (state)
      IDLE: begin
        if (data == 1) begin
          next_state = S1;
        end
        else begin
          next_state = IDLE;
        end
      end
      S1: begin
        if (data == 0) begin
          next_state = S2;
        end
        else begin
          next_state = IDLE;
        end
      end
      S2: begin
        if (data == 0) begin
          next_state = DETECT;
        end
        else begin
          next_state = IDLE;
        end
      end
      DETECT: begin
        detect = 1;
        next_state = IDLE;
      end
    endcase
  end
  
endmodule

其中，`clk` 为时钟输入，`reset` 为复位信号，`data` 为串行输入，`detect` 为检测到序列10010时的输出信号。

状态转换表如下：

| 当前状态 | 输入 | 下一状态 | 输出 |
| :--------: | :----: | :--------: | :----: |
| IDLE | 1 | S1 | 0 |
| IDLE | 0 | IDLE | 0 |
| S1 | 0 | S2 | 0 |
| S1 | 1 | IDLE | 0 |
| S2 | 0 | DETECT | 0 |
| S2 | 1 | IDLE | 0 |
| DETECT | - | IDLE | 1 |