翻译：Description elaborate creates a design hierarchy consisting of a top level design and its referenced subdesigns from the read Verilog/SystemVerilog modules or VHDL entity and architectures. If the top level design is not specified it elaborates all the modules not instantiated by any other module as top level and elaborates them all along with their referenced subdesigns. Elaborate transforms each module/architecture to be represented as a design in the form of a structural netlist. It also performs semantic checking, sequential register (flops/latches) inferencing and high level HDL optimizations. Instances of undefined modules/entities are marked as unresolved and the corresponding modules/entities reported as blackboxes. Users may set the attribute hdl_error_on_latch to true, to error out for latches inferred during elaborate; set the attribute "hdl_error_on_blackbox" to true, to error out for blackboxes during elaborate. The command returns the directory path to the top-level design(s) that it creates. Note: Before elaborating a design, load your library using the library attribute and load your design using the read_hdl command into the Genus shell.

描述：elaborate创建一个设计层次结构，由顶层设计和其引用的子设计组成，从读取的Verilog/SystemVerilog模块或VHDL实体和体系结构中。如果未指定顶层设计，则将所有未由任何其他模块实例化的模块作为顶层进行展开，并展开它们以及其引用的子设计。Elaborate将每个模块/体系结构转换为以结构化网表形式表示的设计。它还执行语义检查、顺序寄存器（flops/latches）推理和高级HDL优化。未定义模块/实体的实例标记为未解决，并报告相应的模块/实体为黑箱。用户可以将属性hdl_error_on_latch设置为true，在展开期间对推断的锁存器报错；将属性"hdl_error_on_blackbox"设置为true，在展开期间对黑箱报错。该命令返回目录路径，指向它创建的顶层设计。注意：在展开设计之前，请使用library属性加载库，并使用read_hdl命令将设计加载到Genus shell中。