IEEE 1801-2015：低功耗电子系统设计与验证的权威标准

2015

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IEEE Standard for Design and Verification of Low-Power (IEEE Std 1801™-2015)，也被称为2015年的修订版，是IEEE Computer Society下的Design Automation Standards Committee发起并制定的一份权威指南，专注于低功耗和能源意识电子系统的设计与验证。这份标准的发布日期为2015年12月5日，经过了IEEE-SA Standards Board的批准，旨在提供一套全面的方法论，帮助工程师们在设计过程中优化能效并确保系统在低功耗模式下仍保持性能。该标准的核心内容涵盖了以下几个关键知识点： 1. **低功耗设计原则**：IEEE Std 1801提供了设计者应遵循的最佳实践，包括电源管理策略、硬件架构优化、以及组件级和系统级的能效考量。它强调了在整个设计流程中考虑能源效率的重要性，从概念阶段到实现和验证。 2. **能量感知电子系统**：标准提倡设计师在系统设计初期就纳入能源管理，通过集成能量感知功能，如动态电压频率调节（DVFS）、电源 gating 和休眠模式，来降低功耗。 3. **工具支持**：标准引用了Accellera Systems Initiative的Unified Power Format (UPF) Version 1.0，这是一种通用的电源格式，用于在硬件描述语言(HDL)设计中统一表示电源行为。此外，还提到了Cadence Design Systems提供的Library Cell Modeling Guide Using CPF，这是一份关于使用Cadence工具进行库细胞模型建模的指南，以支持低功耗设计。 4. **层次化电源意图建模**：Hierarchical Power Intent Modeling (HPI) 是标准中的一项关键技术，它允许设计师在设计的不同层次上定义和传达电源需求，从而简化了整个设计过程，并确保了各部分之间的协同工作。 5. **许可限制**：值得注意的是，标准的使用受到限制，仅限于华中科技大学，并且下载自IEEE Explore时有限制条件。这意味着未经授权的用户可能无法直接使用标准中的全部内容，除非他们获得了相应的许可。 IEEE Std 1801-2015为电子工程师提供了一个框架，使他们在追求高性能的同时，能够有效地管理和优化系统能耗，是设计低功耗电子设备的必备参考资料。对于任何关注能效的电子设计团队来说，理解和遵循这一标准对于提升产品的竞争力和可持续性具有重要意义。

IEEE Std 1801-2015

IEEE Standard for Design and Verification of Low-Power, Energy-Aware Electronic Systems

 A user may further refine the UPF specification to add implementation-related information. This

further-refined specification may then be processed by synthesis tools to produce a netlist and

optionally update the UPF fileset accordingly.

 In those cases where design object names change, a UPF file with the new names is needed. A

UPF-aware logical equivalence checker can read the full design and UPF filesets and perform the

checks to ensure power-aware equivalence.

 Place and route tools read both the netlist and the UPF files and produce a physical netlist,

potentially including an output UPF file.

UPF is a concise, power-intent specification capability. Power intent can be easily specified over many

elements in the design. A UPF specification can be included with the other deliverables of intellectual

property (IP) blocks and reused along with the other delivered IP. UPF supports various methodologies

through carefully defined semantics, flexibility in specification, and, when needed, defined rational

limitations that facilitate automation in verification and implementation.

1.4 Contents of this standard

The organization of the remainder of this standard is as follows:

 Clause 2

provides references to other applicable standards that are presumed or required for this

standard.

 Clause 3 defines terms and acronyms used throughout the different specifications contained in this

standard.

 Clause 4 describes the basic concepts underlying UPF.

 Clause 5 describes the language basics for UPF and its commands.

 Clause 6 details the syntax and semantics for each UPF power intent command.

 Clause 7 details the syntax and semantics for each UPF power-management cell command.

 Clause 8 defines a reference model for UPF command processing.

 Clause 9 defines simulation semantics for various UPF commands.

 Clause 10 defines the UPF information model.

 Clause 11 defines the UPF information model application programmable interface (API).

 Annex A lists potentially useful additional reference material.

 Annex B lists the predefined value conversion tables (VCTs) for use in power intent specifications.

 Annex C provides sample Tcl procs for retrieving power intent information.

 Annex D summarizes deprecated and legacy commands.

 Annex E provides an overview of UPF tool flows and use model with an illustrative example.

 Annex F provdes a summary of UPF power-management cell command semantics and Liberty

mappings.

 Annex G provides examples of UPF power-management cell modeling.

 Annex H provides an overview of UPF use model for system-level IP power modeling.

 Annex I defines the Switching Activity Interchange Format (SAIF) for representing power-related

activity in a design.

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IEEE Std 1801-2015

IEEE Standard for Design and Verification of Low-Power, Energy-Aware Electronic Systems

2. Normative references

The following referenced documents are indispensable for the application of this document (i.e., they must

be understood and used, so each referenced document is cited in text and its relationship to this document is

explained). For dated references, only the edition cited applies. For undated references, the latest edition of

the referenced document (including any amendments or corrigenda) applies.

IEC 61691-1-1/IEEE Std 1076™, Behavioural languages—Part 1-1: VHDL Language Reference Manual.

10, 11,

IEEE Std 1800™, IEEE Standard for SystemVerilog—Unified Hardware Design, Specification, and

Verification Language.

ISO/IEC 19501:2005, Information technology—Open Distributed Processing—Unified Modeling

Language (UML) Version 1.4.2.

3. Definitions, acronyms, and abbreviations

For the purposes of this document, the following terms and definitions apply. The IEEE Standards

Dictionary Online [B1]

should be consulted for terms not defined in this clause.

Certain terms in this

standard reflect their corresponding definitions in IEEE Std 1800™ or IEC 61691-1-1/IEEE Std 1076™, or

they are listed in

Annex A.

3.1 Definitions

active component: A component that contains one or more input receivers and one or more output drivers

whose values are functions of the inputs, but whose inputs and outputs are not directly connected; or any

hardware description language (HDL) construct(s) that synthesize(s) to an active component.

active control signal: A control signal that is currently presenting the value (level) or transition (edge) that

enables or triggers an active component to operate in a particular manner.

active power state: A power state whose logic expression—or, in certain cases, supply expression—

evaluate to True at a given time.

activity: Any change in the value of a net, regardless of whether that change is propagated to an output.

analog port: A port that is part of a connection that delivers analog signals.

ancestor: Any instance between the current scope in the logic hierarchy and its root scope. When the

current scope is a top-level module, it does not have any ancestors. See also: descendant.

anonymous object: An object that is not named in the context of Unified Power Format (UPF).

Implementations may assign a legal name, but such names are not visible in the UPF context.

ISO/IEC publications are available from the International Electrotechnical Commission (http://www.iec.ch/). IEC publications are

also available in the United States from the American National Standards Institute (http://www.ansi.org/).

IEEE publications are available from The Institute of Electrical and Electronics Engineers (http://standards.ieee.org/).

The IEEE standards or products referred to in this clause are trademarks of The Institute of Electrical and Electronics Engineers,

Inc.

The numbers in brackets correspond to those of the bibliography in Annex A.

IEEE Standards Dictionary Online subscription is available at:

http://www.ieee.org/portal/innovate/products/standard/standards_dictionary.html

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IEEE Std 1801-2015

IEEE Standard for Design and Verification of Low-Power, Energy-Aware Electronic Systems

balloon latch: A retention element style in which a register’s value is saved to a dedicated latch at power-

down and the latch value is restored to the register at power-up.

boundary instance: An instance that has no parent or whose parent is in a different power domain.

child domain (of a HighConn port on the lower boundary of a power domain): The power domain

whose upper boundary contains the corresponding LowConn of the HighConn port.

coarse grain switch: A power switch that is used to generate switched supply for a group of library cells.

This is identified using the attribute

switch_cell_type: coarse_grain in Liberty and design attribute

UPF_switch_cell_type coarse_grain in Unified Power Format (UPF) (see Table 4

component: A physical and logical construction that relates inputs to outputs.

composite domain: A power domain consisting of subordinate power domains called subdomains. All

subdomains in a composite domain share the same primary supply set.

configuration UPF: A Unified Power Format (UPF) specification of the power-management configuration

for a system.

connected: Attached together via a direct connection.

constraint UPF: A Unified Power Format (UPF) specification for an intellectual property (IP) block that

defines constraints for any instance of this IP block that must be met by the power-management

configuration of the system containing that instance.

correlated: A pair of supply nets or a pair of supply sets that are deemed to be at the same point in their

voltage range when being considered for level-shifting. As such, when voltage levels are considered

between them they should be mutually compared, e.g., minimum to minimum and maximum to maximum.

corruption semantics: The rules defining the behavior of logic in response to reduction or disconnection

of power to that logic.

current scope: The design hierarchy location that serves as the immediate context for interpretation and

execution of Unified Power Format (UPF) commands. Also, the instance specified by the set_scope

command.

declared: Specified in the hardware description language (HDL) explicitly or implicitly via a Unified

Power Format (UPF) command.

descendant: Any instance between the current scope in the logic hierarchy and its leaf-level instances.

See also: ancestor.

descendant subtree: A portion of a logic hierarchy, rooted at one instance in the hierarchy, and

containing that instance and all of its descendants.

design hierarchy: A hierarchical structure of nested definitions described in a hardware description

language (HDL).

direct connection: A physical wire; or any hardware description language (HDL) construct(s) that

synthesize(s) to a direct connection.

domain port: A port that is on the interface of a power domain.

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IEEE Std 1801-2015

IEEE Standard for Design and Verification of Low-Power, Energy-Aware Electronic Systems

driver: The source or drain of a transistor, if the drain or source is connected to a power rail; a

complementary metal oxide semiconductor (CMOS) inverter that continually connects a node to power or

ground; any component that sets the value of its output via a transistor or inverter; a constant assignment;

any combinational logic including a buffer of any kind; any sequential logic; or any hardware description

language (HDL) construct(s) that synthesize(s) to such combinational or sequential logic.

driver supply: For a driver that is a transistor, the supply connected to its source or drain; for a driver that

is an inverter, the pair of supplies connected to the source/drain of the transistor pair comprising the

inverter; or for an output of an active component, the related supply set of that output.

electrically equivalent: For supply ports/nets, connected (whether the connections are evident or not in

the design) without any intervening switches, and therefore have the same value at all times from the

perspective of any load; for supply sets/set handles, consisting of a set of electrically equivalent supply

nets for each required function.

equivalent: A pair of supply nets, a pair of supply sets or a pair of logic nets that are considered to be

interchangeable for certain purposes. See also: electrically equivalent; functionally equivalent.

erroneous: A usage that is likely to lead to an error in the design, but that tools may not be able to detect

and report.

extent (of a domain): The set of instances that comprise a power domain.

fanout domain (of a given port to which a given strategy applies): The power domain containing any of

the following: receiving logic for that port, or a leaf-level cell instance HighConn input port that is

connected to the given port, or a design top module LowConn output port that is connected to the given

port.

feedthrough: A direct connection between two ports on the interface of a power domain, where the

connection involves two ports on the upper boundary, or two ports on the lower boundary, or one of each;

also, a direction connection between two ports of the same leaf-level instance.

feedthrough port: A port on the interface of a power domain that is part of a feedthrough through that

domain, or a port on the interface of a leaf-level instance that is part of a feedthrough through that

instance.

fine grain switch: A power switch that is used to generate switched supply for a single library cell. This is

typically used to describe embedded macro power switches. This is identified using the attribute

switch_cell_type: fine_grain in Liberty and design attribute UPF_switch_cell_type fine_grain in

Unified Power Format (UPF) (see Table 4

functionally equivalent: Functioning identically from the perspective of any load, either as a result of

being electrically equivalent, or due to independent but parallel circuitry.

generate block: In the hardware description language (HDL) code, this represents a level of design

hierarchy, although a generate block is not itself an instance. After synthesis, generate blocks do not exist

as an independent level of hierarchy. It is illegal to create any Unified Power Format (UPF) objects in a

scope that corresponds to a generate block.

golden source: The design together with the constraint Unified Power Format (UPF) and the configuration

UPF.

hard macro: A block that has been completely implemented and can be used as it is in other blocks. This

can be modeled by an hardware description language (HDL) module for verification or as a library cell for

implementation.

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IEEE Std 1801-2015

IEEE Standard for Design and Verification of Low-Power, Energy-Aware Electronic Systems

hierarchical name: A series of names separated by the hierarchical separator character, the final name

of which is a legal hardware description language (HDL) name or Unified Power Format (UPF) name, and

each preceding name is the name of an instance or generate block in which the following name is

declared. See also: hierarchical separator character.

hierarchical separator character: A special character used in composing hierarchical names. The

hierarchical separator character is a slash (/).

HighConn: The side of a port connection that is higher in the design hierarchy; the actual signal

associated with a formal port definition.

implementation UPF: The Unified Power Format (UPF) specification of how power distribution and

control is to be implemented for a system.

inactive: A normally active component in a state in which it does not respond to activity on its inputs.

Also, a control signal that is not currently presenting the value (level) or transition (edge) that enables or

triggers an active component to operate in a particular manner.

instance: A particular occurrence of a SystemVerilog module (see IEEE Std 1800), very high speed

integrated circuit (VHSIC) hardware description language (VHDL) entity (see IEC 61691-1-1/IEEE Std

1076), or library cell at a specific location within the design hierarchy.

interface of a power domain: The union of the upper boundary and the lower boundary of the power

domain.

isolation: A technique used to provide defined behavior of a logic signal when its driving logic is not

active.

isolation cell: An instance that passes logic values during normal mode operation and clamps its output to

some specified logic value when a control signal is asserted.

leaf-level cell: An instance that has no descendants, or an instance that is a soft or hard macro.

leaf-level instance: See: leaf-level cell.

level-shifter: An instance that translates signal values from an input voltage swing to a different output

voltage swing.

live slave: A retention element style in which the slave latch of a master-slave flip-flop (MSFF) is always

on and therefore maintains the value of the MSFF during power-down.

logically equivalent: Logic ports/nets that are directly connected without any intervening logic and

therefore have the same value at all times from the perspective of any sink.

logic hierarchy: An abstract view of a design hierarchy in which only those definitions representing

instances are included.

LowConn: The side of a port connection that is lower in the design hierarchy; the formal port definition.

lower boundary (of a power domain): The HighConn side of each port of each boundary instance in

the extent of another power domain whose parent is in the extent of this domain, together with the

HighConn side of each port of any macro cell instance in this power domain, for which the related supply

set is neither identical to nor equivalent to the primary supply set of this domain.

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