PCI Express Base Specification 4.0 Rev 0.7: 2016年更新

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"PCI Express Base Specification Revision 4.0 Version 0.7 February, 2016" PCI Express（Peripheral Component Interconnect Express，简称PCIe）是一种高速接口标准，用于计算机系统中的设备间通信，如显卡、网卡、硬盘等。此文档是PCI Express基线规范的第4.0版本，修订号0.7，发布于2016年2月，是当时公开的最新版本。 PCIe规范的各个修订版本主要关注性能提升和新功能的添加。以下是对这些修订历史的详细解释： 1.0：这是最初的发布版本，奠定了PCI Express的基础架构和协议，定义了2.5 GT/s的数据速率，提供了比传统PCI和PCI-X更高的带宽。 1.0a：在1.0版本的基础上，整合了错误（Errata）C1-C66和E1-E4.17的修正，提升了规范的稳定性和兼容性。 1.1：这一版本进一步包含了批准的错误修正和工程变更通知（ECNs），确保了设备之间的互操作性和可靠性。 2.0：在此版本中，数据速率翻倍至5.0 GT/s，显著提高了传输速度。同时，也整合了新的错误修正和ECNs。 2.1：除了整合2.0版的错误修正，还增加了几个ECNs，包括内部错误报告、多播、原子操作、可调整大小的BAR（基址寄存器）能力、动态功率分配、基于ID的排序、延迟容忍度报告、替代路由ID解释（ARI）、扩展标签启用默认、TLP处理提示和TLP前缀等。这些改进增强了系统的效率、错误处理能力和功能多样性。 3.x系列的版本未在摘要中提及，但通常会继续提高数据速率和引入新特性，例如PCIe 3.0达到了8 GT/s，而PCIe 3.1和3.2则主要关注增强和优化。 4.0：此版本的亮点在于将数据速率提升至16 GT/s，即每个通道的带宽翻倍到16 GB/s，双通道（x16）接口的总带宽可达32 GB/s。此外，还可能包含对功耗管理、错误恢复和信号完整性等方面的改进。 PCI Express的每个版本升级都是为了满足不断增长的高性能计算和数据传输需求，提供更高的带宽、更低的延迟和更强的系统稳定性。4.0版本的发布标志着PCIe技术的一个重要里程碑，为数据中心、服务器、存储和高端消费级硬件等领域带来了更快的数据交换速度。

PCI EXPRESS BASE SPECIFICATION, REV. 4.0 VERSION 0.7

8.4.2 Electrical Idle........................................................................................................ 1026

8.4.3 EIEOS for M-PCIe ................................................................................................ 1026

8.4.4 Lane Polarity Inversion ........................................................................................ 1026

8.4.5 Fast Training Sequence (FTS) .............................................................................. 1026

8.4.6 LINK Data RATE .................................................................................................. 1027

8.4.7 LINK Width ........................................................................................................... 1027

8.4.8 LANE-to-LANE De-skew ...................................................................................... 1027

8.4.9 LINK Training and Status State Machine (LTSSM) ............................................. 1027

8.4.10 Entry to HIBERN8 ............................................................................................ 1049

8.5 RECEIVER ERROR ....................................................................................................... 1049

8.6 CLOCK TOLERANCE COMPENSATION ......................................................................... 1050

8.7 DYNAMIC LINK BANDWIDTH MANAGEMENT ........................................................... 1050

8.7.1 LINK Rate Series and Speed Management ........................................................... 1050

8.7.2 LINK Width Management ..................................................................................... 1051

8.7.3 Dynamic LINK Re-Configuration ......................................................................... 1051

8.8 M-PHY REGISTERS ................................................................................................... 1054

8.8.1 M-PHY Capability Registers................................................................................. 1054

8.8.2 M-PHY Configuration Attributes .......................................................................... 1061

9 ELECTRICAL SUB-BLOCK ....................................................................................... 1063

9.1 ELECTRICAL SPECIFICATION ORGANIZATION ............................................................ 1063

9.2 INTEROPERABILITY CRITERIA .................................................................................... 1063

9.2.1 Data Rates ............................................................................................................. 1063

9.2.2 Refclk Architectures .............................................................................................. 1063

9.3 TRANSMITTER SPECIFICATION ................................................................................... 1063

9.3.1 Measurement Setup for Characterizing Transmitters........................................... 1063

9.3.2 Voltage Level Definitions ...................................................................................... 1065

9.3.3 Tx Voltage Parameters ......................................................................................... 1066

9.3.4 Transmitter Margining.......................................................................................... 1075

9.3.5 Tx Jitter Parameters ............................................................................................. 1076

9.3.6 Tx and Rx Return Loss .......................................................................................... 1086

9.3.7 Transmitter PLL Bandwidth and Peaking ............................................................ 1088

9.3.8 Data Rate Independent Tx Parameters ................................................................. 1088

9.4 RECEIVER SPECIFICATIONS ........................................................................................ 1090

9.4.1 Receiver Stressed Eye Specification ..................................................................... 1090

9.4.2 Stressed Eye Test................................................................................................... 1095

9.4.3 Common Receiver Parameters ............................................................................. 1102

9.4.4 Low Frequency and Miscellaneous Signaling Requirements ............................... 1105

9.5 CHANNEL TOLERANCING ........................................................................................... 1107

9.5.1 Channel Compliance Testing ................................................................................ 1107

9.6 REFCLK SPECIFICATIONS ........................................................................................... 1116

9.6.1 Refclk Test Setup ................................................................................................... 1116

9.6.2 Data Rate Independent Refclk Parameters ........................................................... 1117

9.6.3 Refclk Architectures Supported............................................................................. 1118

9.6.4 Filtering Functions Applied to Raw Data ............................................................. 1118

9.6.5 Common Refclk Rx Architecture (CC) .................................................................. 1120

9.6.6 Jitter Limits for Refclk Architectures .................................................................... 1123

PCI EXPRESS BASE SPECIFICATION, REV. 4.0 VERSION 0.7

10 SR-IOV SPECIFICATION ............................................................................................ 1124

10.1 ARCHITECTURAL OVERVIEW ..................................................................................... 1124

10.1.1 PCI Technologies Interoperability ................................................................... 1136

10.2 INITIALIZATION AND RESOURCE ALLOCATION .......................................................... 1137

10.2.1 SR-IOV Resource Discovery ............................................................................. 1137

10.2.2 Reset Mechanisms ............................................................................................. 1141

10.2.3 IOV Re-initialization and Reallocation ............................................................ 1142

10.2.4 VF Migration .................................................................................................... 1142

10.3 CONFIGURATION ........................................................................................................ 1145

10.3.1 Overview ........................................................................................................... 1145

10.3.2 Configuration Space ......................................................................................... 1146

10.3.3 SR-IOV Extended Capability ............................................................................ 1146

10.3.4 PF/VF Configuration Space Header ................................................................ 1161

10.3.5 PCI Express Capability..................................................................................... 1166

10.3.6 PCI Standard Capabilities ................................................................................ 1174

10.3.7 PCI Express Extended Capabilities .................................................................. 1175

10.4 ERROR HANDLING ..................................................................................................... 1181

10.4.1 Baseline Error Reporting .................................................................................. 1181

10.4.2 Advanced Error Reporting ................................................................................ 1183

10.5 INTERRUPTS ............................................................................................................... 1190

10.5.1 Interrupt Mechanisms ....................................................................................... 1190

10.6 POWER MANAGEMENT ............................................................................................... 1191

10.6.1 VF Device Power Management States .............................................................. 1191

10.6.2 PF Device Power Management States .............................................................. 1191

10.6.3 Link Power Management State ......................................................................... 1192

10.6.4 VF Power Management Capability .................................................................. 1192

SR-IOV ACKNOWLEDGEMENTS ............................................................................................ 1192

11 ATS SPECIFICATION .................................................................................................. 1195

11.1 ARCHITECTURAL OVERVIEW ..................................................................................... 1195

11.1.1 Address Translation Services (ATS) Overview ................................................. 1197

11.1.2 Page Request Interface Extension .................................................................... 1202

11.1.3 Process Address Space ID (PASID) ................................................................. 1204

11.2 ATS TRANSLATION SERVICES ................................................................................... 1205

11.2.1 Memory Requests with Address Type ............................................................... 1205

11.2.2 Translation Requests ......................................................................................... 1206

11.2.3 Translation Completion .................................................................................... 1209

11.2.4 Completions with Multiple Translations ........................................................... 1216

11.3 ATS INVALIDATION ................................................................................................... 1218

11.3.1 Invalidate Request ............................................................................................. 1218

11.3.2 Invalidate Completion ....................................................................................... 1219

11.3.3 Invalidate Completion Semantics ..................................................................... 1221

11.3.4 Request Acceptance Rules................................................................................. 1222

11.3.5 Invalidate Flow Control .................................................................................... 1222

11.3.6 Invalidate Ordering Semantics ......................................................................... 1223

11.3.7 Implicit Invalidation Events .............................................................................. 1224

PCI EXPRESS BASE SPECIFICATION, REV. 4.0 VERSION 0.7

11.3.8 PASID TLP Prefix and Global Invalidate ........................................................ 1225

11.4 PAGE REQUEST SERVICES .......................................................................................... 1226

11.4.1 Page Request Message ...................................................................................... 1227

11.4.2 Page Request Group Response Message .......................................................... 1231

11.5 CONFIGURATION ........................................................................................................ 1233

11.5.1 ATS Extended Capability Structure .................................................................. 1233

11.5.2 Page Request Extended Capability Structure ................................................... 1236

ATS ACKNOWLEDGEMENTS .................................................................................................. 1242

A. ISOCHRONOUS APPLICATIONS ................................................................................. 1255

A.1. INTRODUCTION .......................................................................................................... 1255

A.2. ISOCHRONOUS CONTRACT AND CONTRACT PARAMETERS ......................................... 1257

A.2.1. Isochronous Time Period and Isochronous Virtual Timeslot ........................... 1258

A.2.2. Isochronous Payload Size ................................................................................. 1259

A.2.3. Isochronous Bandwidth Allocation ................................................................... 1259

A.2.4. Isochronous Transaction Latency ..................................................................... 1260

A.2.5. An Example Illustrating Isochronous Parameters ............................................ 1261

A.3. ISOCHRONOUS TRANSACTION RULES ......................................................................... 1262

A.4. TRANSACTION ORDERING .......................................................................................... 1262

A.5. ISOCHRONOUS DATA COHERENCY ............................................................................. 1262

A.6. FLOW CONTROL ......................................................................................................... 1263

A.7. CONSIDERATIONS FOR BANDWIDTH ALLOCATION ..................................................... 1263

A.7.1. Isochronous Bandwidth of PCI Express Links.................................................. 1263

A.7.2. Isochronous Bandwidth of Endpoints ............................................................... 1263

A.7.3. Isochronous Bandwidth of Switches ................................................................. 1263

A.7.4. Isochronous Bandwidth of Root Complex......................................................... 1264

A.8. CONSIDERATIONS FOR PCI EXPRESS COMPONENTS ................................................... 1264

A.8.1. An Endpoint as a Requester .............................................................................. 1264

A.8.2. An Endpoint as a Completer ............................................................................. 1264

A.8.3. Switches............................................................................................................. 1265

A.8.4. Root Complex .................................................................................................... 1266

B. SYMBOL ENCODING .................................................................................................... 1267

C. PHYSICAL LAYER APPENDIX .................................................................................... 1276

C.1. 8B/10B DATA SCRAMBLING EXAMPLE ....................................................................... 1276

C.2. 128B/130B DATA SCRAMBLING EXAMPLE ................................................................. 1282

D. REQUEST DEPENDENCIES .......................................................................................... 1285

E. ID-BASED ORDERING USAGE .................................................................................... 1288

E.1. INTRODUCTION .......................................................................................................... 1288

E.2. POTENTIAL BENEFITS WITH IDO USE ........................................................................ 1289

E.2.1. Benefits for MFD/RP Direct Connect ............................................................... 1289

E.2.2. Benefits for Switched Environments ................................................................. 1289

E.2.3. Benefits for Integrated Endpoints ..................................................................... 1290

E.2.4. IDO Use in Conjunction with RO ..................................................................... 1290

E.3. WHEN TO USE IDO .................................................................................................... 1290

PCI EXPRESS BASE SPECIFICATION, REV. 4.0 VERSION 0.7

E.4. WHEN NOT TO USE IDO ............................................................................................ 1291

E.4.1. When Not to Use IDO with Endpoints .............................................................. 1291

E.4.2. When Not to Use IDO with Root Ports ............................................................. 1291

E.5. SOFTWARE CONTROL OF IDO USE ............................................................................. 1292

E.5.1. Software Control of Endpoint IDO Use ............................................................ 1292

E.5.2. Software Control of Root Port IDO Use ........................................................... 1293

F. MESSAGE CODE USAGE .............................................................................................. 1294

G. PROTOCOL MULTIPLEXING ................................................................................... 1296

G.1. PROTOCOL MULTIPLEXING INTERACTIONS WITH PCI EXPRESS ................................. 1299

G.2. PMUX PACKETS ........................................................................................................ 1305

G.3. PMUX PACKET LAYOUT ........................................................................................... 1306

G.3.1. PMUX Packet Layout for 8b10b Encoding ...................................................... 1306

G.3.2. PMUX Packet Layout at 128b/130b Encoding ................................................. 1308

G.4. PMUX CONTROL ....................................................................................................... 1311

G.5. PMUX EXTENDED CAPABILITY ................................................................................. 1311

G.5.1. PCI Express Extended Header (Offset 00h) ..................................................... 1312

G.5.2. PMUX Capability Register (Offset 04h) ........................................................... 1313

G.5.3. PMUX Control Register (Offset 08h) ............................................................... 1314

G.5.4. PMUX Status Register (Offset 0Ch) ................................................................. 1316

G.5.5. PMUX Protocol Array (Offsets 10h Through 48h) ........................................... 1319

H. M-PCIE TIMING DIAGRAMS .................................................................................... 1321

H.1. INIT TO L0 .................................................................................................................. 1322

H.2. L0 WITH TRANSMITTER IN STALL ............................................................................ 1323

H.3. L0 TO L1 .................................................................................................................... 1324

H.4. DOWNSTREAM PORT INITIATED LINK BANDWIDTH CHANGE ................................... 1325

H.5. UPSTREAM PORT INITIATED LINK BANDWIDTH CHANGE ......................................... 1326

I. M-PCIE COMPLIANCE PATTERNS ......................................................................... 1327

I.1. RPAT ........................................................................................................................ 1327

I.2. RPAT VARIATION BY LANE ...................................................................................... 1328

I.3. CONTINUOUS MODE CRPAT ..................................................................................... 1328

I.4. BURST MODE CRPAT ............................................................................................... 1329

ACKNOWLEDGEMENTS ...................................................................................................... 1330

PCI EXPRESS BASE SPECIFICATION, REV. 4.0 VERSION 0.7

Figures

FIGURE 1-1: PCI EXPRESS LINK .................................................................................................... 59

FIGURE 1-2: EXAMPLE TOPOLOGY ................................................................................................ 60

FIGURE 1-3: LOGICAL BLOCK DIAGRAM OF A SWITCH ................................................................. 64

FIGURE 1-4: HIGH-LEVEL LAYERING DIAGRAM ........................................................................... 66

FIGURE 1-5: PACKET FLOW THROUGH THE LAYERS ..................................................................... 67

FIGURE 2-1: LAYERING DIAGRAM HIGHLIGHTING THE TRANSACTION LAYER .............................. 72

FIGURE 2-2: SERIAL VIEW OF A TLP ............................................................................................. 75

FIGURE 2-3: GENERIC TLP FORMAT ............................................................................................. 76

FIGURE 2-4: FIELDS PRESENT IN ALL TLPS .................................................................................. 77

FIGURE 2-5: FIELDS PRESENT IN ALL TLP HEADERS .................................................................... 78

FIGURE 2-6: EXAMPLES OF COMPLETER TARGET MEMORY ACCESS FOR FETCHADD ................... 83

FIGURE 2-7: 64-BIT ADDRESS ROUTING ........................................................................................ 85

FIGURE 2-8: 32-BIT ADDRESS ROUTING ........................................................................................ 85

FIGURE 2-9: ID ROUTING WITH 4 DW HEADER ............................................................................ 88

FIGURE 2-10: ID ROUTING WITH 3 DW HEADER .......................................................................... 88

FIGURE 2-11: LOCATION OF BYTE ENABLES IN TLP HEADER ....................................................... 89

FIGURE 2-12: TRANSACTION DESCRIPTOR .................................................................................... 92

FIGURE 2-13: TRANSACTION ID .................................................................................................... 92

FIGURE 2-14: ATTRIBUTES FIELD OF TRANSACTION DESCRIPTOR ................................................ 99

FIGURE 2-15: REQUEST HEADER FORMAT FOR 64-BIT ADDRESSING OF MEMORY ...................... 102

FIGURE 2-16: REQUEST HEADER FORMAT FOR 32-BIT ADDRESSING OF MEMORY ...................... 102

FIGURE 2-17: REQUEST HEADER FORMAT FOR I/O TRANSACTIONS ............................................ 103

FIGURE 2-18: REQUEST HEADER FORMAT FOR CONFIGURATION TRANSACTIONS ...................... 104

FIGURE 2-192: TPH TLP PREFIX ................................................................................................ 105

FIGURE 2-20: LOCATION OF PH[1:0] IN A 4 DW REQUEST HEADER ........................................... 106

FIGURE 2-21: LOCATION OF PH[1:0] IN A 3 DW REQUEST HEADER ........................................... 106

FIGURE 2-22: LOCATION OF ST[7:0] IN THE MEMORY WRITE REQUEST HEADER ....................... 108

FIGURE 2-23: LOCATION OF ST[7:0] IN MEMORY READ AND ATOMICOP REQUEST HEADERS ... 108

FIGURE 2-24: MESSAGE REQUEST HEADER ................................................................................ 110

FIGURE 2-25: HEADER FOR VENDOR-DEFINED MESSAGES ......................................................... 120

FIGURE 2-26: HEADER FOR PCI-SIG-DEFINED VDMS ................................................................ 121

FIGURE 2-27: LN MESSAGE [TO BE UPDATED] ............................................................................ 123

FIGURE 2-28: DRS MESSAGE ...................................................................................................... 124

FIGURE 2-29: FRS MESSAGE ...................................................................................................... 125

FIGURE 2-30: LTR MESSAGE ...................................................................................................... 127

FIGURE 2-31: OBFF MESSAGE ................................................................................................... 128

FIGURE 2-32: PTM REQUEST/RESPONSE MESSAGE ..................................................................... 129

FIGURE 2-33: PTM RESPONSED MESSAGE (4 DW HEADER AND 1 DW PAYLOAD) ...................... 130

FIGURE 2-34: COMPLETION HEADER FORMAT ............................................................................ 132

FIGURE 2-35: (NON-ARI) COMPLETER ID .................................................................................. 133

FIGURE 2-36: ARI COMPLETER ID .............................................................................................. 133

FIGURE 2-37: FLOWCHART FOR HANDLING OF RECEIVED TLPS ................................................. 140

FIGURE 2-38: FLOWCHART FOR SWITCH HANDLING OF TLPS ..................................................... 142

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