"PCI-SIG发布PCI-Express® 6.0.1基础规范"

PCIe

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"PCI-Express-Base-6.0.1 协议是由PCI-SIG发布的一项针对PCI Express®接口的基本规范，该规范旨在为PCI Express®技术的应用提供统一的标准。NCB-PCI_Express_Base_6.0.1版本为PCI Express® Base Specification Revision 6.0.1，版权归PCI-SIG所有。然而，PCI-SIG对于该规范及其中所含信息的使用不承担任何担保责任，并对该规范中可能出现的任何错误不承担责任，也不作出更新的承诺。此规范及规范中所含信息均为“现状”提供，不包括任何形式的任何担保，包括但不限于适销性、非侵权、适用于任何特定目的等方面的担保。" "该规范的推出旨在为PCI Express®技术的发展提供统一的规范标准，从而促进相关产品的开发和应用。PCI Express®技术作为一种高速串行接口技术，在计算机领域具有广泛的应用，例如在图形处理器、网络接口卡和存储设备等方面都有所体现。PCI Express®技术的不断推陈出新，也带来了对相关规范的不断更新和完善，以适应新的应用场景和技术发展趋势。因此，NCB-PCI_Express_Base_6.0.1规范的发布将为PCI Express®技术的发展提供更可靠的技术支持和规范引导。" "然而，作为一项技术规范，PCI-Express-Base-6.0.1 协议的推出也需要在实际应用中不断进行验证和调整。由于技术的不断推陈出新，相关产品和设备也在不断更新和演变，因此需要不断对规范进行修订和更新，以确保其与市场需求和技术发展趋势保持一致。同时，技术规范的制定也需要充分考虑各方利益的平衡，既要保证规范的权威性和可靠性，又要避免过于僵化和牵制技术创新的发展。因此，PCI-SIG作为规范的发布方，需要在规范的制定和更新过程中充分听取各方的意见和建议，确保规范的合理性和可行性。" "综上所述，PCI-Express-Base-6.0.1协议作为PCI Express®接口的基本规范，是PCI-SIG为促进PCI Express®技术发展而推出的统一标准。该规范的发布将为PCI Express®技术的应用和产品开发提供更可靠的技术支撑和规范引导。然而，规范的制定和更新需要充分考虑市场需求和技术发展趋势，并在实际应用中不断进行验证和调整，以确保其与市场需求和技术发展趋势的一致性。希望PCI-SIG能够在规范的制定和更新过程中充分考虑各方的意见和建议，使得该规范能够更好地适应市场需求和技术发展趋势。"

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7.5.1 PCI-Compatible Configuration Registers ............................................................................................................... 921

7.5.1.1 Type 0/1 Common Configuration Space ........................................................................................................ 921

7.5.1.1.1 Vendor ID Register (Oset 00h)............................................................................................................... 922

7.5.1.1.2 Device ID Register (Oset 02h)................................................................................................................ 923

7.5.1.1.3 Command Register (Oset 04h) ............................................................................................................. 923

7.5.1.1.4 Status Register (Oset 06h)..................................................................................................................... 926

7.5.1.1.5 Revision ID Register (Oset 08h)............................................................................................................. 928

7.5.1.1.6 Class Code Register (Oset 09h)............................................................................................................. 928

7.5.1.1.7 Cache Line Size Register (Oset 0Ch)..................................................................................................... 929

7.5.1.1.8 Latency Timer Register (Oset 0Dh)....................................................................................................... 929

7.5.1.1.9 Header Type Register (Oset 0Eh).......................................................................................................... 929

7.5.1.1.10 BIST Register (Oset 0Fh) ....................................................................................................................... 930

7.5.1.1.11 Capabilities Pointer (Oset 34h)............................................................................................................. 931

7.5.1.1.12 Interrupt Line Register (Oset 3Ch)........................................................................................................ 931

7.5.1.1.13 Interrupt Pin Register (Oset 3Dh) ......................................................................................................... 932

7.5.1.1.14 Error Registers ......................................................................................................................................... 932

7.5.1.2 Type 0 Configuration Space Header............................................................................................................... 933

7.5.1.2.1 Base Address Registers (Oset 10h - 24h) .............................................................................................. 933

7.5.1.2.2 Cardbus CIS Pointer Register (Oset 28h).............................................................................................. 936

7.5.1.2.3 Subsystem Vendor ID Register/Subsystem ID Register (Oset 2Ch/2Eh) ............................................. 937

7.5.1.2.4 Expansion ROM Base Address Register (Oset 30h) .............................................................................. 937

7.5.1.2.5 Min_Gnt Register/Max_Lat Register (Oset 3Eh/3Fh) ........................................................................... 940

7.5.1.3 Type 1 Configuration Space Header............................................................................................................... 940

7.5.1.3.1 Type 1 Base Address Registers (Oset 10h-14h).................................................................................... 941

7.5.1.3.2 Primary Bus Number Register (Oset 18h) ............................................................................................ 942

7.5.1.3.3 Secondary Bus Number Register (Oset 19h)........................................................................................ 942

7.5.1.3.4 Subordinate Bus Number Register (Oset 1Ah)..................................................................................... 942

7.5.1.3.5 Secondary Latency Timer (Oset 1Bh) .................................................................................................. 942

7.5.1.3.6 I/O Base/I/O Limit Registers(Oset 1Ch/1Dh)........................................................................................ 942

7.5.1.3.7 Secondary Status Register (Oset 1Eh).................................................................................................. 943

7.5.1.3.8 Memory Base Register/Memory Limit Register(Oset 20h/22h)........................................................... 945

7.5.1.3.9 Prefetchable Memory Base/Prefetchable Memory Limit Registers (Oset 24h/26h) .......................... 945

7.5.1.3.10 Prefetchable Base Upper 32 Bits/Prefetchable Limit Upper 32 Bits Registers (Oset 28h/2Ch)......... 946

7.5.1.3.11 I/O Base Upper 16 Bits/I/O Limit Upper 16 Bits Registers (Oset 30h/32h).......................................... 946

7.5.1.3.12 Expansion ROM Base Address Register (Oset 38h) .............................................................................. 947

7.5.1.3.13 Bridge Control Register (Oset 3Eh)....................................................................................................... 947

7.5.2 PCI Power Management Capability Structure........................................................................................................ 949

7.5.2.1 Power Management Capabilities Register (Oset 00h)................................................................................. 950

7.5.2.2 Power Management Control/Status Register (Oset 04h) ............................................................................ 952

7.5.2.3 Power Management Data Register (Oset 07h) ............................................................................................. 954

7.5.3 PCI Express Capability Structure ............................................................................................................................ 956

7.5.3.1 PCI Express Capability List Register (Oset 00h) ........................................................................................... 957

7.5.3.2 PCI Express Capabilities Register (Oset 02h) ............................................................................................... 957

7.5.3.3 Device Capabilities Register (Oset 04h) ....................................................................................................... 959

7.5.3.4 Device Control Register (Oset 08h)............................................................................................................... 963

7.5.3.5 Device Status Register (Oset 0Ah) ................................................................................................................ 970

7.5.3.6 Link Capabilities Register (Oset 0Ch)........................................................................................................... 971

7.5.3.7 Link Control Register (Oset 10h)................................................................................................................... 975

7.5.3.8 Link Status Register (Oset 12h)..................................................................................................................... 982

7.5.3.9 Slot Capabilities Register (Oset 14h)............................................................................................................ 985

6.0.1-1.0-PUB — PCI Express® Base Specification Revision 6.0.1

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Base 6.0.1 (Base 6.0 plus Errata as of 2022-08-29)

7.5.3.10 Slot Control Register (Oset 18h) ................................................................................................................... 987

7.5.3.11 Slot Status Register (Oset 1Ah)..................................................................................................................... 990

7.5.3.12 Root Control Register (Oset 1Ch) ................................................................................................................. 992

7.5.3.13 Root Capabilities Register (Oset 1Eh) .......................................................................................................... 994

7.5.3.14 Root Status Register (Oset 20h).................................................................................................................... 994

7.5.3.15 Device Capabilities 2 Register (Oset 24h)..................................................................................................... 996

7.5.3.16 Device Control 2 Register (Oset 28h).......................................................................................................... 1001

7.5.3.17 Device Status 2 Register (Oset 2Ah)............................................................................................................ 1004

7.5.3.18 Link Capabilities 2 Register (Oset 2Ch) ...................................................................................................... 1005

7.5.3.19 Link Control 2 Register (Oset 30h).............................................................................................................. 1008

7.5.3.20 Link Status 2 Register (Oset 32h)................................................................................................................ 1011

7.5.3.21 Slot Capabilities 2 Register (Oset 34h) ....................................................................................................... 1014

7.5.3.22 Slot Control 2 Register (Oset 38h) .............................................................................................................. 1015

7.5.3.23 Slot Status 2 Register (Oset 3Ah) ................................................................................................................ 1015

7.6 PCI Express Extended Capabilities ............................................................................................................................... 1015

7.6.1 Extended Capabilities in Configuration Space..................................................................................................... 1015

7.6.2 Extended Capabilities in the Root Complex Register Block ................................................................................ 1015

7.6.3 PCI Express Extended Capability Header ............................................................................................................. 1016

7.7 PCI and PCIe Capabilities Required by the Base Spec in Some Situations ................................................................ 1016

7.7.1 MSI Capability Structures...................................................................................................................................... 1016

7.7.1.1 MSI Capability Header (Oset 00h) .............................................................................................................. 1018

7.7.1.2 Message Control Register for MSI (Oset 02h)............................................................................................. 1019

7.7.1.3 Message Address Register for MSI (Oset 04h) ............................................................................................ 1021

7.7.1.4 Message Upper Address Register for MSI (Oset 08h)................................................................................. 1021

7.7.1.5 Message Data Register for MSI (Oset 08h or 0Ch) ...................................................................................... 1022

7.7.1.6 Extended Message Data Register for MSI (Optional).................................................................................... 1022

7.7.1.7 Mask Bits Register for MSI (Oset 0Ch or 10h .............................................................................................. 1023

7.7.1.8 Pending Bits Register for MSI (Oset 10h or 14h) ........................................................................................ 1023

7.7.2 MSI-X Capability and Table Structure................................................................................................................... 1024

7.7.2.1 MSI-X Capability Header (Oset 00h) ........................................................................................................... 1027

7.7.2.2 Message Control Register for MSI-X (Oset 02h).......................................................................................... 1028

7.7.2.3 Table Oset/Table BIR Register for MSI-X (Oset 04h) ................................................................................ 1029

7.7.2.4 PBA Oset/PBA BIR Register for MSI-X (Oset 08h) ..................................................................................... 1029

7.7.2.5 Message Address Register for MSI-X Table Entries....................................................................................... 1030

7.7.2.6 Message Upper Address Register for MSI-X Table Entries............................................................................ 1031

7.7.2.7 Message Data Register for MSI-X Table Entries ............................................................................................ 1031

7.7.2.8 Vector Control Register for MSI-X Table Entries ........................................................................................... 1031

7.7.2.9 Pending Bits Register for MSI-X PBA Entries ................................................................................................ 1032

7.7.3 Secondary PCI Express Extended Capability........................................................................................................ 1033

7.7.3.1 Secondary PCI Express Extended Capability Header (Oset 00h) .............................................................. 1035

7.7.3.2 Link Control 3 Register (Oset 04h).............................................................................................................. 1035

7.7.3.3 Lane Error Status Register (Oset 08h) ........................................................................................................ 1036

7.7.3.4 Lane Equalization Control Register (Oset 0Ch).......................................................................................... 1037

7.7.4 Data Link Feature Extended Capability ................................................................................................................ 1039

7.7.4.1 Data Link Feature Extended Capability Header (Oset 00h)....................................................................... 1040

7.7.4.2 Data Link Feature Capabilities Register (Oset 04h) ................................................................................... 1041

7.7.4.3 Data Link Feature Status Register (Oset 08h)............................................................................................. 1042

7.7.5 Physical Layer 16.0 GT/s Extended Capability...................................................................................................... 1043

7.7.5.1 Physical Layer 16.0 GT/s Extended Capability Header (Oset 00h) ............................................................ 1045

7.7.5.2 16.0 GT/s Capabilities Register (Oset 04h) .............................................................................................. 1045

6.0.1-1.0-PUB — PCI Express® Base Specification Revision 6.0.1

Page 17

Base 6.0.1 (Base 6.0 plus Errata as of 2022-08-29)

7.7.5.3 16.0 GT/s Control Register (Oset 08h) ..................................................................................................... 1046

7.7.5.4 16.0 GT/s Status Register (Oset 0Ch) ....................................................................................................... 1046

7.7.5.5 16.0 GT/s Local Data Parity Mismatch Status Register (Oset 10h).......................................................... 1047

7.7.5.6 16.0 GT/s First Retimer Data Parity Mismatch Status Register (Oset 14h) ............................................. 1048

7.7.5.7 16.0 GT/s Second Retimer Data Parity Mismatch Status Register (Oset 18h)........................................ 1048

7.7.5.8 Physical Layer 16.0 GT/s Reserved (Oset 1Ch)........................................................................................... 1049

7.7.5.9 16.0 GT/s Lane Equalization Control Register (Osets 20h to 3Ch).......................................................... 1049

7.7.6 Physical Layer 32.0 GT/s Extended Capability...................................................................................................... 1050

7.7.6.1 Physical Layer 32.0 GT/s Extended Capability Header (Oset 00h) ............................................................ 1052

7.7.6.2 32.0 GT/s Capabilities Register (Oset 04h) .............................................................................................. 1052

7.7.6.3 32.0 GT/s Control Register (Oset 08h) ..................................................................................................... 1053

7.7.6.4 32.0 GT/s Status Register (Oset 0Ch) ....................................................................................................... 1054

7.7.6.5 Received Modified TS Data 1 Register (Oset 10h) ...................................................................................... 1055

7.7.6.6 Received Modified TS Data 2 Register (Oset 14h) ...................................................................................... 1056

7.7.6.7 Transmitted Modified TS Data 1 Register (Oset 18h)................................................................................. 1057

7.7.6.8 Transmitted Modified TS Data 2 Register (Oset 1Ch)................................................................................. 1058

7.7.6.9 32.0 GT/s Lane Equalization Control Register (Oset 20h)....................................................................... 1059

7.7.7 Physical Layer 64.0 GT/s Extended Capability...................................................................................................... 1061

7.7.7.1 Physical Layer 64.0 GT/s Extended Capability Header (Oset 00h) ............................................................ 1062

7.7.7.2 64.0 GT/s Capabilities Register (Oset 04h) .............................................................................................. 1062

7.7.7.3 64.0 GT/s Control Register (Oset 08h) ..................................................................................................... 1063

7.7.7.4 64.0 GT/s Status Register (Oset 0Ch) ....................................................................................................... 1063

7.7.7.5 64.0 GT/s Lane Equalization Control Register (Oset 20h)....................................................................... 1064

7.7.8 Flit Logging Extended Capability.......................................................................................................................... 1066

7.7.8.1 Flit Logging Extended Capability Header (Oset 00h)................................................................................. 1066

7.7.8.2 Flit Error Log 1 Register (Oset 04h)............................................................................................................. 1067

7.7.8.3 Flit Error Log 2 Register (Oset 08h)............................................................................................................. 1069

7.7.8.4 Flit Error Counter Control Register (Oset 0Ch) .......................................................................................... 1070

7.7.8.5 Flit Error Counter Status Register (Oset 0Eh)............................................................................................. 1071

7.7.8.6 FBER Measurement Control Register (Oset 10h) ....................................................................................... 1072

7.7.8.7 FBER Measurement Status 1 Register (Oset 14h) ...................................................................................... 1073

7.7.8.8 FBER Measurement Status 2 Register (Oset 18h) ...................................................................................... 1073

7.7.8.9 FBER Measurement Status 3 Register (Oset 1Ch) ...................................................................................... 1074

7.7.8.10 FBER Measurement Status 4 Register (Oset 20h) ...................................................................................... 1074

7.7.8.11 FBER Measurement Status 5 Register (Oset 24h) ...................................................................................... 1075

7.7.8.12 FBER Measurement Status 6 Register (Oset 28h) ...................................................................................... 1075

7.7.8.13 FBER Measurement Status 7 Register (Oset 2Ch) ...................................................................................... 1075

7.7.8.14 FBER Measurement Status 8 Register (Oset 30h) ...................................................................................... 1076

7.7.8.15 FBER Measurement Status 9 Register (Oset 34h) ...................................................................................... 1076

7.7.8.16 FBER Measurement Status 10 Register (Oset 38h) .................................................................................... 1077

7.7.9 Device 3 Extended Capability Structure ............................................................................................................... 1077

7.7.9.1 Device 3 Extended Capability Header (Oset 00h) ...................................................................................... 1077

7.7.9.2 Device Capabilities 3 Register (Oset 04h)................................................................................................... 1078

7.7.9.3 Device Control 3 Register (Oset 08h).......................................................................................................... 1080

7.7.9.4 Device Status 3 Register (Oset 0Ch)............................................................................................................ 1082

7.7.10 Lane Margining at the Receiver Extended Capability .......................................................................................... 1083

7.7.10.1 Lane Margining at the Receiver Extended Capability Header (Oset 00h)................................................. 1085

7.7.10.2 Margining Port Capabilities Register (Oset 04h)........................................................................................ 1085

7.7.10.3 Margining Port Status Register (Oset 06h) ................................................................................................. 1086

7.7.10.4 Margining Lane Control Register (Oset 08h).............................................................................................. 1086

6.0.1-1.0-PUB — PCI Express® Base Specification Revision 6.0.1

Page 18

Base 6.0.1 (Base 6.0 plus Errata as of 2022-08-29)

7.7.10.5 Margining Lane Status Register (Oset 0Ah)................................................................................................ 1087

7.7.11 ACS Extended Capability....................................................................................................................................... 1088

7.7.11.1 ACS Extended Capability Header (Oset 00h).............................................................................................. 1089

7.7.11.2 ACS Capability Register (Oset 04h)............................................................................................................. 1090

7.7.11.3 ACS Control Register (Oset 06h) ................................................................................................................. 1091

7.7.11.4 Egress Control Vector Register (Oset 08h) ................................................................................................. 1093

7.8 Common PCI and PCIe Capabilities ............................................................................................................................. 1095

7.8.1 Power Budgeting Extended Capability................................................................................................................. 1095

7.8.1.1 Power Budgeting Extended Capability Header (Oset 00h)........................................................................ 1095

7.8.1.2 Power Budgeting Data Select Register (Oset 04h)..................................................................................... 1096

7.8.1.3 Power Budgeting Control Register (Oset 06h) ........................................................................................... 1096

7.8.1.4 Power Budgeting Data Register (Oset 08h)................................................................................................ 1098

7.8.1.5 Power Budgeting Capability Register (Oset 0Ch) ...................................................................................... 1103

7.8.1.6 Power Budgeting Sense Detect Register (Oset 0Dh) ................................................................................. 1104

7.8.2 Latency Tolerance Reporting (LTR) Extended Capability..................................................................................... 1106

7.8.2.1 LTR Extended Capability Header (Oset 00h) .............................................................................................. 1107

7.8.2.2 Max Snoop Latency Register (Oset 04h)..................................................................................................... 1107

7.8.2.3 Max No-Snoop Latency Register (Oset 06h)............................................................................................... 1108

7.8.3 L1 PM Substates Extended Capability .................................................................................................................. 1108

7.8.3.1 L1 PM Substates Extended Capability Header (Oset 00h) ......................................................................... 1109

7.8.3.2 L1 PM Substates Capabilities Register (Oset 04h) ..................................................................................... 1110

7.8.3.3 L1 PM Substates Control 1 Register (Oset 08h).......................................................................................... 1111

7.8.3.4 L1 PM Substates Control 2 Register (Oset 0Ch) ......................................................................................... 1113

7.8.3.5 L1 PM Substates Status Register (Oset 10h)............................................................................................... 1114

7.8.4 Advanced Error Reporting Extended Capability .................................................................................................. 1114

7.8.4.1 Advanced Error Reporting Extended Capability Header (Oset 00h)......................................................... 1117

7.8.4.2 Uncorrectable Error Status Register (Oset 04h)......................................................................................... 1117

7.8.4.3 Uncorrectable Error Mask Register (Oset 08h)........................................................................................... 1119

7.8.4.4 Uncorrectable Error Severity Register (Oset 0Ch) ..................................................................................... 1121

7.8.4.5 Correctable Error Status Register (Oset 10h)............................................................................................. 1123

7.8.4.6 Correctable Error Mask Register (Oset 14h)............................................................................................... 1124

7.8.4.7 Advanced Error Capabilities and Control Register (Oset 18h) .................................................................. 1125

7.8.4.8 Header Log Register (Oset 1Ch).................................................................................................................. 1127

7.8.4.9 Root Error Command Register (Oset 2Ch) ................................................................................................. 1128

7.8.4.10 Root Error Status Register (Oset 30h)......................................................................................................... 1129

7.8.4.11 Error Source Identification Register (Oset 34h)......................................................................................... 1131

7.8.4.12 TLP Prefix Log Register (Oset 38h) ............................................................................................................. 1132

7.8.5 Enhanced Allocation Capability Structure (EA) ................................................................................................... 1133

7.8.5.1 Enhanced Allocation Capability First DW (Oset 00h)................................................................................. 1133

7.8.5.2 Enhanced Allocation Capability Second DW (Oset 04h)

[Type 1 Functions Only] ................................................................................................................................ 1134

7.8.5.3 Enhanced Allocation Per-Entry Format (Oset 04h or 08h) ........................................................................ 1134

7.8.6 Resizable BAR Extended Capability...................................................................................................................... 1139

7.8.6.1 Resizable BAR Extended Capability Header (Oset 00h)............................................................................. 1142

7.8.6.2 Resizable BAR Capability Register ................................................................................................................ 1142

7.8.6.3 Resizable BAR Control Register .................................................................................................................... 1145

7.8.7 VF Resizable BAR Extended Capability ................................................................................................................. 1147

7.8.7.1 VF Resizable BAR Extended Capability Header (Oset 00h)........................................................................ 1149

7.8.7.2 VF Resizable BAR Capability Register (Oset 04h)....................................................................................... 1149

7.8.7.3 VF Resizable BAR Control Register (Oset 08h) ........................................................................................... 1149

6.0.1-1.0-PUB — PCI Express® Base Specification Revision 6.0.1

Page 19

Base 6.0.1 (Base 6.0 plus Errata as of 2022-08-29)

7.8.8 ARI Extended Capability........................................................................................................................................ 1151

7.8.8.1 ARI Extended Capability Header (Oset 00h)............................................................................................... 1151

7.8.8.2 ARI Capability Register (Oset 04h).............................................................................................................. 1152

7.8.8.3 ARI Control Register (Oset 06h) .................................................................................................................. 1153

7.8.9 PASID Extended Capability Structure................................................................................................................... 1153

7.8.9.1 PASID Extended Capability Header (Oset 00h) .......................................................................................... 1154

7.8.9.2 PASID Capability Register (Oset 04h) ......................................................................................................... 1154

7.8.9.3 PASID Control Register (Oset 06h).............................................................................................................. 1155

7.8.10 FRS Queueing Extended Capability...................................................................................................................... 1157

7.8.10.1 FRS Queueing Extended Capability Header (Oset 00h)............................................................................. 1157

7.8.10.2 FRS Queueing Capability Register (Oset 04h)............................................................................................ 1158

7.8.10.3 FRS Queueing Status Register (Oset 08h) .................................................................................................. 1158

7.8.10.4 FRS Queueing Control Register (Oset 0Ah) ................................................................................................ 1159

7.8.10.5 FRS Message Queue Register (Oset 0Ch).................................................................................................... 1159

7.8.11 Flattening Portal Bridge (FPB) Capability ............................................................................................................ 1160

7.8.11.1 FPB Capability Header (Oset 00h).............................................................................................................. 1161

7.8.11.2 FPB Capabilities Register (Oset 04h).......................................................................................................... 1161

7.8.11.3 FPB RID Vector Control 1 Register (Oset 08h) ............................................................................................ 1163

7.8.11.4 FPB RID Vector Control 2 Register (Oset 0Ch)............................................................................................ 1164

7.8.11.5 FPB MEM Low Vector Control Register (Oset 10h) ..................................................................................... 1165

7.8.11.6 FPB MEM High Vector Control 1 Register (Oset 14h) ................................................................................. 1166

7.8.11.7 FPB MEM High Vector Control 2 Register (Oset 18h) ................................................................................. 1168

7.8.11.8 FPB Vector Access Control Register (Oset 1Ch) ......................................................................................... 1169

7.8.11.9 FPB Vector Access Data Register (Oset 20h)............................................................................................... 1170

7.8.12 Flit Performance Measurement Extended Capability.......................................................................................... 1171

7.8.12.1 Flit Performance Measurement Extended Capability Header (Oset 00h)................................................. 1171

7.8.12.2 Flit Performance Measurement Capability Register (Oset 04h)................................................................ 1172

7.8.12.3 Flit Performance Measurement Control Register (Oset 08h) .................................................................... 1173

7.8.12.4 Flit Performance Measurement Status Register (Oset 0Ch)...................................................................... 1175

7.8.12.5 LTSSM Performance Measurement Status Register (Osets 10h to 20h) .................................................... 1175

7.8.13 Flit Error Injection Extended Capability ............................................................................................................... 1176

7.8.13.1 Flit Error Injection Extended Capability Header (Oset 00h) ...................................................................... 1177

7.8.13.2 Flit Error Injection Capability Register (Oset 04h) ..................................................................................... 1178

7.8.13.3 Flit Error Injection Control 1 Register (Oset 08h)....................................................................................... 1178

7.8.13.4 Flit Error Injection Control 2 Register (Oset 0Ch) ...................................................................................... 1180

7.8.13.5 Flit Error Injection Status Register (Oset 10h)............................................................................................ 1181

7.8.13.6 Ordered Set Error Injection Control 1 Register (Oset 14h) ........................................................................ 1182

7.8.13.7 Ordered Set Error Injection Control 2 Register (Oset 18h) ........................................................................ 1183

7.8.13.8 Ordered Set Error Tx Injection Status Register (Oset 1Ch)........................................................................ 1184

7.8.13.9 Ordered Set Error Rx Injection Status Register (Oset 20h) ........................................................................ 1185

7.9 Additional PCI and PCIe Capabilities............................................................................................................................ 1186

7.9.1 Virtual Channel Extended Capability.................................................................................................................... 1186

7.9.1.1 Virtual Channel Extended Capability Header (Oset 00h) .......................................................................... 1187

7.9.1.2 Port VC Capability Register 1 (Oset 04h) .................................................................................................... 1188

7.9.1.3 Port VC Capability Register 2 (Oset 08h) .................................................................................................... 1189

7.9.1.4 Port VC Control Register (Oset 0Ch) ........................................................................................................... 1190

7.9.1.5 Port VC Status Register (Oset 0Eh) ............................................................................................................. 1191

7.9.1.6 VC Resource Capability Register................................................................................................................... 1191

7.9.1.7 VC Resource Control Register ....................................................................................................................... 1193

7.9.1.8 VC Resource Status Register ......................................................................................................................... 1195

6.0.1-1.0-PUB — PCI Express® Base Specification Revision 6.0.1

Page 20

Base 6.0.1 (Base 6.0 plus Errata as of 2022-08-29)